diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon')
6 files changed, 14 insertions, 15 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 31c43b0cd74..cd482b3e3af 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -72,7 +72,7 @@ HexagonSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS) { HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) - : HexagonGenSubtargetInfo(TargetTuple(TT), CPU, FS), CPUString(CPU), + : HexagonGenSubtargetInfo(TT, CPU, FS), CPUString(CPU), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), FrameLowering() { diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp index 105e78f3cb9..99ea2fabf86 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp @@ -309,7 +309,7 @@ public: namespace llvm { MCAsmBackend *createHexagonAsmBackend(Target const &T, MCRegisterInfo const & /*MRI*/, - const TargetTuple &TT, StringRef CPU) { + const Triple &TT, StringRef CPU) { uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); return new HexagonAsmBackend(T, OSABI, CPU); } diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp index 113b622a4f0..51d2f1c878d 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.cpp @@ -18,7 +18,7 @@ using namespace llvm; // Pin the vtable to this file. void HexagonMCAsmInfo::anchor() {} -HexagonMCAsmInfo::HexagonMCAsmInfo(const TargetTuple &TT) { +HexagonMCAsmInfo::HexagonMCAsmInfo(const Triple &TT) { Data16bitsDirective = "\t.half\t"; Data32bitsDirective = "\t.word\t"; Data64bitsDirective = nullptr; // .xword is only supported by V9. diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h index de9702ea789..a8456b4ead9 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCAsmInfo.h @@ -18,13 +18,13 @@ #include "llvm/MC/MCAsmInfoELF.h" namespace llvm { -class TargetTuple; +class Triple; class HexagonMCAsmInfo : public MCAsmInfoELF { void anchor() override; public: - explicit HexagonMCAsmInfo(const TargetTuple &TT); + explicit HexagonMCAsmInfo(const Triple &TT); }; } // namespace llvm diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp index ca426345187..53305d85fd8 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.cpp @@ -46,15 +46,14 @@ MCInstrInfo *llvm::createHexagonMCInstrInfo() { return X; } -static MCRegisterInfo *createHexagonMCRegisterInfo(const TargetTuple &TT) { +static MCRegisterInfo *createHexagonMCRegisterInfo(const Triple &TT) { MCRegisterInfo *X = new MCRegisterInfo(); InitHexagonMCRegisterInfo(X, Hexagon::R0); return X; } -static MCSubtargetInfo *createHexagonMCSubtargetInfo(const TargetTuple &TT, - StringRef CPU, - StringRef FS) { +static MCSubtargetInfo * +createHexagonMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createHexagonMCSubtargetInfoImpl(TT, CPU, FS); } @@ -139,7 +138,7 @@ public: } static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, - const TargetTuple &TT) { + const Triple &TT) { MCAsmInfo *MAI = new HexagonMCAsmInfo(TT); // VirtualFP = (R30 + #0). @@ -150,7 +149,7 @@ static MCAsmInfo *createHexagonMCAsmInfo(const MCRegisterInfo &MRI, return MAI; } -static MCCodeGenInfo *createHexagonMCCodeGenInfo(const TargetTuple &TT, +static MCCodeGenInfo *createHexagonMCCodeGenInfo(const Triple &TT, Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL) { @@ -161,7 +160,7 @@ static MCCodeGenInfo *createHexagonMCCodeGenInfo(const TargetTuple &TT, return X; } -static MCInstPrinter *createHexagonMCInstPrinter(const TargetTuple &TT, +static MCInstPrinter *createHexagonMCInstPrinter(const Triple &T, unsigned SyntaxVariant, const MCAsmInfo &MAI, const MCInstrInfo &MII, @@ -179,7 +178,7 @@ static MCTargetStreamer *createMCAsmTargetStreamer(MCStreamer &S, return new HexagonTargetAsmStreamer(S, OS, IsVerboseAsm, *InstPrint); } -static MCStreamer *createMCStreamer(const TargetTuple &TT, MCContext &Context, +static MCStreamer *createMCStreamer(Triple const &T, MCContext &Context, MCAsmBackend &MAB, raw_pwrite_stream &OS, MCCodeEmitter *Emitter, bool RelaxAll) { return createHexagonELFStreamer(Context, MAB, OS, Emitter); diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h index a5c23bdfdaa..cb626503313 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCTargetDesc.h @@ -27,7 +27,7 @@ class MCObjectWriter; class MCRegisterInfo; class MCSubtargetInfo; class Target; -class TargetTuple; +class Triple; class StringRef; class raw_ostream; class raw_pwrite_stream; @@ -44,7 +44,7 @@ MCCodeEmitter *createHexagonMCCodeEmitter(MCInstrInfo const &MCII, MCAsmBackend *createHexagonAsmBackend(Target const &T, MCRegisterInfo const &MRI, - const TargetTuple &TT, StringRef CPU); + const Triple &TT, StringRef CPU); MCObjectWriter *createHexagonELFObjectWriter(raw_pwrite_stream &OS, uint8_t OSABI, StringRef CPU); |
