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-rw-r--r--llvm/lib/Target/Hexagon/BitTracker.cpp15
-rw-r--r--llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp31
-rw-r--r--llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp32
-rw-r--r--llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp27
-rw-r--r--llvm/lib/Target/Hexagon/HexagonGenInsert.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp4
-rw-r--r--llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp18
-rw-r--r--llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp14
-rw-r--r--llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp4
-rw-r--r--llvm/lib/Target/Hexagon/HexagonPeephole.cpp5
-rw-r--r--llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/RDFGraph.cpp10
-rw-r--r--llvm/lib/Target/Hexagon/RDFGraph.h2
-rw-r--r--llvm/lib/Target/Hexagon/RDFLiveness.cpp4
16 files changed, 89 insertions, 85 deletions
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp
index 4a10408d8c7..a8b89990277 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/BitTracker.cpp
@@ -767,7 +767,7 @@ bool BT::MachineEvaluator::evaluate(const MachineInstr &MI,
void BT::visitPHI(const MachineInstr &PI) {
int ThisN = PI.getParent()->getNumber();
if (Trace)
- dbgs() << "Visit FI(BB#" << ThisN << "): " << PI;
+ dbgs() << "Visit FI(" << printMBBReference(*PI.getParent()) << "): " << PI;
const MachineOperand &MD = PI.getOperand(0);
assert(MD.getSubReg() == 0 && "Unexpected sub-register in definition");
@@ -784,7 +784,8 @@ void BT::visitPHI(const MachineInstr &PI) {
const MachineBasicBlock *PB = PI.getOperand(i + 1).getMBB();
int PredN = PB->getNumber();
if (Trace)
- dbgs() << " edge BB#" << PredN << "->BB#" << ThisN;
+ dbgs() << " edge " << printMBBReference(*PB) << "->"
+ << printMBBReference(*PI.getParent());
if (!EdgeExec.count(CFGEdge(PredN, ThisN))) {
if (Trace)
dbgs() << " not executable\n";
@@ -809,10 +810,8 @@ void BT::visitPHI(const MachineInstr &PI) {
}
void BT::visitNonBranch(const MachineInstr &MI) {
- if (Trace) {
- int ThisN = MI.getParent()->getNumber();
- dbgs() << "Visit MI(BB#" << ThisN << "): " << MI;
- }
+ if (Trace)
+ dbgs() << "Visit MI(" << printMBBReference(*MI.getParent()) << "): " << MI;
if (MI.isDebugValue())
return;
assert(!MI.isBranch() && "Unexpected branch instruction");
@@ -897,7 +896,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
BTs.clear();
const MachineInstr &MI = *It;
if (Trace)
- dbgs() << "Visit BR(BB#" << ThisN << "): " << MI;
+ dbgs() << "Visit BR(" << printMBBReference(B) << "): " << MI;
assert(MI.isBranch() && "Expecting branch instruction");
InstrExec.insert(&MI);
bool Eval = ME.evaluate(MI, Map, BTs, FallsThrough);
@@ -913,7 +912,7 @@ void BT::visitBranchesFrom(const MachineInstr &BI) {
if (Trace) {
dbgs() << " adding targets:";
for (unsigned i = 0, n = BTs.size(); i < n; ++i)
- dbgs() << " BB#" << BTs[i]->getNumber();
+ dbgs() << " " << printMBBReference(*BTs[i]);
if (FallsThrough)
dbgs() << "\n falls through\n";
else
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index d3cb53e3594..f14beaad339 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -2977,7 +2977,7 @@ void HexagonLoopRescheduling::moveGroup(InstrGroup &G, MachineBasicBlock &LB,
}
bool HexagonLoopRescheduling::processLoop(LoopCand &C) {
- DEBUG(dbgs() << "Processing loop in BB#" << C.LB->getNumber() << "\n");
+ DEBUG(dbgs() << "Processing loop in " << printMBBReference(*C.LB) << "\n");
std::vector<PhiInfo> Phis;
for (auto &I : *C.LB) {
if (!I.isPHI())
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index 9a8762a48fd..80db36071db 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -617,7 +617,7 @@ void MachineConstPropagator::CellMap::print(raw_ostream &os,
void MachineConstPropagator::visitPHI(const MachineInstr &PN) {
const MachineBasicBlock *MB = PN.getParent();
unsigned MBN = MB->getNumber();
- DEBUG(dbgs() << "Visiting FI(BB#" << MBN << "): " << PN);
+ DEBUG(dbgs() << "Visiting FI(" << printMBBReference(*MB) << "): " << PN);
const MachineOperand &MD = PN.getOperand(0);
Register DefR(MD);
@@ -642,8 +642,8 @@ Bottomize:
const MachineBasicBlock *PB = PN.getOperand(i+1).getMBB();
unsigned PBN = PB->getNumber();
if (!EdgeExec.count(CFGEdge(PBN, MBN))) {
- DEBUG(dbgs() << " edge BB#" << PBN << "->BB#" << MBN
- << " not executable\n");
+ DEBUG(dbgs() << " edge " << printMBBReference(*PB) << "->"
+ << printMBBReference(*MB) << " not executable\n");
continue;
}
const MachineOperand &SO = PN.getOperand(i);
@@ -658,9 +658,8 @@ Bottomize:
LatticeCell SrcC;
bool Eval = MCE.evaluate(UseR, Cells.get(UseR.Reg), SrcC);
- DEBUG(dbgs() << " edge from BB#" << PBN << ": "
- << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg)
- << SrcC << '\n');
+ DEBUG(dbgs() << " edge from " << printMBBReference(*PB) << ": "
+ << printReg(UseR.Reg, &MCE.TRI, UseR.SubReg) << SrcC << '\n');
Changed |= Eval ? DefC.meet(SrcC)
: DefC.setBottom();
Cells.update(DefR.Reg, DefC);
@@ -672,7 +671,7 @@ Bottomize:
}
void MachineConstPropagator::visitNonBranch(const MachineInstr &MI) {
- DEBUG(dbgs() << "Visiting MI(BB#" << MI.getParent()->getNumber()
+ DEBUG(dbgs() << "Visiting MI(" << printMBBReference(*MI.getParent())
<< "): " << MI);
CellMap Outputs;
bool Eval = MCE.evaluate(MI, Cells, Outputs);
@@ -729,8 +728,8 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) {
while (It != End) {
const MachineInstr &MI = *It;
InstrExec.insert(&MI);
- DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "(BB#"
- << MBN << "): " << MI);
+ DEBUG(dbgs() << "Visiting " << (EvalOk ? "BR" : "br") << "("
+ << printMBBReference(B) << "): " << MI);
// Do not evaluate subsequent branches if the evaluation of any of the
// previous branches failed. Keep iterating over the branches only
// to mark them as executable.
@@ -772,7 +771,8 @@ void MachineConstPropagator::visitBranchesFrom(const MachineInstr &BrI) {
for (const MachineBasicBlock *TB : Targets) {
unsigned TBN = TB->getNumber();
- DEBUG(dbgs() << " pushing edge BB#" << MBN << " -> BB#" << TBN << "\n");
+ DEBUG(dbgs() << " pushing edge " << printMBBReference(B) << " -> "
+ << printMBBReference(*TB) << "\n");
FlowQ.push(CFGEdge(MBN, TBN));
}
}
@@ -870,8 +870,10 @@ void MachineConstPropagator::propagate(MachineFunction &MF) {
CFGEdge Edge = FlowQ.front();
FlowQ.pop();
- DEBUG(dbgs() << "Picked edge BB#" << Edge.first << "->BB#"
- << Edge.second << '\n');
+ DEBUG(dbgs() << "Picked edge "
+ << printMBBReference(*MF.getBlockNumbered(Edge.first)) << "->"
+ << printMBBReference(*MF.getBlockNumbered(Edge.second))
+ << '\n');
if (Edge.first != EntryNum)
if (EdgeExec.count(Edge))
continue;
@@ -934,7 +936,8 @@ void MachineConstPropagator::propagate(MachineFunction &MF) {
for (const MachineBasicBlock *SB : B.successors()) {
unsigned SN = SB->getNumber();
if (!EdgeExec.count(CFGEdge(BN, SN)))
- dbgs() << " BB#" << BN << " -> BB#" << SN << '\n';
+ dbgs() << " " << printMBBReference(B) << " -> "
+ << printMBBReference(*SB) << '\n';
}
}
});
@@ -3126,7 +3129,7 @@ bool HexagonConstEvaluator::rewriteHexBranch(MachineInstr &BrI,
if (BrI.getOpcode() == Hexagon::J2_jump)
return false;
- DEBUG(dbgs() << "Rewrite(BB#" << B.getNumber() << "):" << BrI);
+ DEBUG(dbgs() << "Rewrite(" << printMBBReference(B) << "):" << BrI);
bool Rewritten = false;
if (NumTargets > 0) {
assert(!FallsThru && "This should have been checked before");
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index 4a6100d02fc..652ea13c414 100644
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -27,24 +27,24 @@
//
// %40<def> = L2_loadrub_io %39<kill>, 1
// %41<def> = S2_tstbit_i %40<kill>, 0
-// J2_jumpt %41<kill>, <BB#5>, %pc<imp-def,dead>
-// J2_jump <BB#4>, %pc<imp-def,dead>
-// Successors according to CFG: BB#4(62) BB#5(62)
+// J2_jumpt %41<kill>, <%bb.5>, %pc<imp-def,dead>
+// J2_jump <%bb.4>, %pc<imp-def,dead>
+// Successors according to CFG: %bb.4(62) %bb.5(62)
//
-// BB#4: derived from LLVM BB %if.then
-// Predecessors according to CFG: BB#3
+// %bb.4: derived from LLVM BB %if.then
+// Predecessors according to CFG: %bb.3
// %11<def> = A2_addp %6, %10
// S2_storerd_io %32, 16, %11
-// Successors according to CFG: BB#5
+// Successors according to CFG: %bb.5
//
-// BB#5: derived from LLVM BB %if.end
-// Predecessors according to CFG: BB#3 BB#4
-// %12<def> = PHI %6, <BB#3>, %11, <BB#4>
+// %bb.5: derived from LLVM BB %if.end
+// Predecessors according to CFG: %bb.3 %bb.4
+// %12<def> = PHI %6, <%bb.3>, %11, <%bb.4>
// %13<def> = A2_addp %7, %12
// %42<def> = C2_cmpeqi %9, 10
-// J2_jumpf %42<kill>, <BB#3>, %pc<imp-def,dead>
-// J2_jump <BB#6>, %pc<imp-def,dead>
-// Successors according to CFG: BB#6(4) BB#3(124)
+// J2_jumpf %42<kill>, <%bb.3>, %pc<imp-def,dead>
+// J2_jump <%bb.6>, %pc<imp-def,dead>
+// Successors according to CFG: %bb.6(4) %bb.3(124)
//
// would become:
//
@@ -55,9 +55,9 @@
// %46<def> = PS_pselect %41, %6, %11
// %13<def> = A2_addp %7, %46
// %42<def> = C2_cmpeqi %9, 10
-// J2_jumpf %42<kill>, <BB#3>, %pc<imp-def,dead>
-// J2_jump <BB#6>, %pc<imp-def,dead>
-// Successors according to CFG: BB#6 BB#3
+// J2_jumpf %42<kill>, <%bb.3>, %pc<imp-def,dead>
+// J2_jump <%bb.6>, %pc<imp-def,dead>
+// Successors according to CFG: %bb.6 %bb.3
#include "Hexagon.h"
#include "HexagonInstrInfo.h"
@@ -238,7 +238,7 @@ bool HexagonEarlyIfConversion::isPreheader(const MachineBasicBlock *B) const {
bool HexagonEarlyIfConversion::matchFlowPattern(MachineBasicBlock *B,
MachineLoop *L, FlowPattern &FP) {
- DEBUG(dbgs() << "Checking flow pattern at BB#" << B->getNumber() << "\n");
+ DEBUG(dbgs() << "Checking flow pattern at " << printMBBReference(*B) << "\n");
// Interested only in conditional branches, no .new, no new-value, etc.
// Check the terminators directly, it's easier than handling all responses
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index 86645ddf913..78c7c102e7d 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -654,7 +654,7 @@ bool HexagonExpandCondsets::split(MachineInstr &MI,
return false;
TfrCounter++;
}
- DEBUG(dbgs() << "\nsplitting BB#" << MI.getParent()->getNumber() << ": "
+ DEBUG(dbgs() << "\nsplitting " << printMBBReference(*MI.getParent()) << ": "
<< MI);
MachineOperand &MD = MI.getOperand(0); // Definition
MachineOperand &MP = MI.getOperand(1); // Predicate register
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index ebb7add82e1..a6a950ea045 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -443,7 +443,7 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
DEBUG({
dbgs() << "Blocks needing SF: {";
for (auto &B : SFBlocks)
- dbgs() << " BB#" << B->getNumber();
+ dbgs() << " " << printMBBReference(*B);
dbgs() << " }\n";
});
// No frame needed?
@@ -464,12 +464,16 @@ void HexagonFrameLowering::findShrunkPrologEpilog(MachineFunction &MF,
break;
}
DEBUG({
- dbgs() << "Computed dom block: BB#";
- if (DomB) dbgs() << DomB->getNumber();
- else dbgs() << "<null>";
- dbgs() << ", computed pdom block: BB#";
- if (PDomB) dbgs() << PDomB->getNumber();
- else dbgs() << "<null>";
+ dbgs() << "Computed dom block: ";
+ if (DomB)
+ dbgs() << printMBBReference(*DomB);
+ else
+ dbgs() << "<null>";
+ dbgs() << ", computed pdom block: ";
+ if (PDomB)
+ dbgs() << printMBBReference(*PDomB);
+ else
+ dbgs() << "<null>";
dbgs() << "\n";
});
if (!DomB || !PDomB)
@@ -2010,7 +2014,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
auto P = BlockIndexes.insert(
std::make_pair(&B, HexagonBlockRanges::InstrIndexMap(B)));
auto &IndexMap = P.first->second;
- DEBUG(dbgs() << "Index map for BB#" << B.getNumber() << "\n"
+ DEBUG(dbgs() << "Index map for " << printMBBReference(B) << "\n"
<< IndexMap << '\n');
for (auto &In : B) {
@@ -2129,7 +2133,8 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
else
dbgs() << "<null>\n";
for (auto &R : P.second.Map)
- dbgs() << " BB#" << R.first->getNumber() << " { " << R.second << "}\n";
+ dbgs() << " " << printMBBReference(*R.first) << " { " << R.second
+ << "}\n";
}
});
@@ -2162,7 +2167,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
auto &FIs = P.second;
if (FIs.empty())
continue;
- dbgs() << " BB#" << P.first->getNumber() << ": {";
+ dbgs() << " " << printMBBReference(*P.first) << ": {";
for (auto I : FIs) {
dbgs() << " fi#" << I;
if (LoxFIs.count(I))
@@ -2183,7 +2188,7 @@ void HexagonFrameLowering::optimizeSpillSlots(MachineFunction &MF,
HexagonBlockRanges::InstrIndexMap &IM = F->second;
HexagonBlockRanges::RegToRangeMap LM = HBR.computeLiveMap(IM);
HexagonBlockRanges::RegToRangeMap DM = HBR.computeDeadMap(IM, LM);
- DEBUG(dbgs() << "BB#" << B.getNumber() << " dead map\n"
+ DEBUG(dbgs() << printMBBReference(B) << " dead map\n"
<< HexagonBlockRanges::PrintRangeMap(DM, HRI));
for (auto FI : BlockFIMap[&B]) {
diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
index d1f63699292..99f3a2e9e88 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -915,7 +915,7 @@ bool HexagonGenInsert::findRecordInsertForms(unsigned VR,
void HexagonGenInsert::collectInBlock(MachineBasicBlock *B,
OrderedRegisterList &AVs) {
if (isDebug())
- dbgs() << "visiting block BB#" << B->getNumber() << "\n";
+ dbgs() << "visiting block " << printMBBReference(*B) << "\n";
// First, check if this block is reachable at all. If not, the bit tracker
// will not have any information about registers in it.
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index 5c18cc8732d..b5fa0689d04 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1011,7 +1011,7 @@ bool HexagonHardwareLoops::isInvalidLoopOperation(const MachineInstr *MI,
bool HexagonHardwareLoops::containsInvalidInstruction(MachineLoop *L,
bool IsInnerHWLoop) const {
const std::vector<MachineBasicBlock *> &Blocks = L->getBlocks();
- DEBUG(dbgs() << "\nhw_loop head, BB#" << Blocks[0]->getNumber(););
+ DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0]));
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
MachineBasicBlock *MBB = Blocks[i];
for (MachineBasicBlock::iterator
@@ -1367,7 +1367,7 @@ bool HexagonHardwareLoops::isLoopFeeder(MachineLoop *L, MachineBasicBlock *A,
LoopFeederMap &LoopFeederPhi) const {
if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) {
const std::vector<MachineBasicBlock *> &Blocks = L->getBlocks();
- DEBUG(dbgs() << "\nhw_loop head, BB#" << Blocks[0]->getNumber(););
+ DEBUG(dbgs() << "\nhw_loop head, " << printMBBReference(*Blocks[0]));
// Ignore all BBs that form Loop.
for (unsigned i = 0, e = Blocks.size(); i != e; ++i) {
MachineBasicBlock *MBB = Blocks[i];
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index 4cdfd09c095..cb00bc770c0 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -463,7 +463,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
Cond.push_back(LastInst->getOperand(1));
return false;
}
- DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
+ DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
<< " with one jump\n";);
// Otherwise, don't know what this is.
return true;
@@ -511,7 +511,7 @@ bool HexagonInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
FBB = LastInst->getOperand(0).getMBB();
return false;
}
- DEBUG(dbgs() << "\nCant analyze BB#" << MBB.getNumber()
+ DEBUG(dbgs() << "\nCant analyze " << printMBBReference(MBB)
<< " with two jumps";);
// Otherwise, can't handle this.
return true;
@@ -521,7 +521,7 @@ unsigned HexagonInstrInfo::removeBranch(MachineBasicBlock &MBB,
int *BytesRemoved) const {
assert(!BytesRemoved && "code size not handled");
- DEBUG(dbgs() << "\nRemoving branches out of BB#" << MBB.getNumber());
+ DEBUG(dbgs() << "\nRemoving branches out of " << printMBBReference(MBB));
MachineBasicBlock::iterator I = MBB.end();
unsigned Count = 0;
while (I != MBB.begin()) {
@@ -593,7 +593,7 @@ unsigned HexagonInstrInfo::insertBranch(MachineBasicBlock &MBB,
// (ins IntRegs:$src1, IntRegs:$src2, brtarget:$offset)
// (ins IntRegs:$src1, u5Imm:$src2, brtarget:$offset)
unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
- DEBUG(dbgs() << "\nInserting NVJump for BB#" << MBB.getNumber(););
+ DEBUG(dbgs() << "\nInserting NVJump for " << printMBBReference(MBB););
if (Cond[2].isReg()) {
unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
@@ -829,9 +829,8 @@ void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
#ifndef NDEBUG
// Show the invalid registers to ease debugging.
- dbgs() << "Invalid registers for copy in BB#" << MBB.getNumber()
- << ": " << printReg(DestReg, &HRI)
- << " = " << printReg(SrcReg, &HRI) << '\n';
+ dbgs() << "Invalid registers for copy in " << printMBBReference(MBB) << ": "
+ << printReg(DestReg, &HRI) << " = " << printReg(SrcReg, &HRI) << '\n';
#endif
llvm_unreachable("Unimplemented");
}
@@ -4032,8 +4031,9 @@ void HexagonInstrInfo::immediateExtend(MachineInstr &MI) const {
bool HexagonInstrInfo::invertAndChangeJumpTarget(
MachineInstr &MI, MachineBasicBlock *NewTarget) const {
- DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to BB#"
- << NewTarget->getNumber(); MI.dump(););
+ DEBUG(dbgs() << "\n[invertAndChangeJumpTarget] to "
+ << printMBBReference(*NewTarget);
+ MI.dump(););
assert(MI.isBranch());
unsigned NewOpcode = getInvertedPredicatedOpcode(MI.getOpcode());
int TargetPos = MI.getNumOperands() - 1;
diff --git a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
index 5daceac6496..8765fc98448 100644
--- a/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonMachineScheduler.cpp
@@ -186,12 +186,10 @@ bool VLIWResourceModel::reserveResources(SUnit *SU) {
/// after setting up the current scheduling region. [RegionBegin, RegionEnd)
/// only includes instructions that have DAG nodes, not scheduling boundaries.
void VLIWMachineScheduler::schedule() {
- DEBUG(dbgs()
- << "********** MI Converging Scheduling VLIW BB#" << BB->getNumber()
- << " " << BB->getName()
- << " in_func " << BB->getParent()->getFunction()->getName()
- << " at loop depth " << MLI->getLoopDepth(BB)
- << " \n");
+ DEBUG(dbgs() << "********** MI Converging Scheduling VLIW "
+ << printMBBReference(*BB) << " " << BB->getName() << " in_func "
+ << BB->getParent()->getFunction()->getName() << " at loop depth "
+ << MLI->getLoopDepth(BB) << " \n");
buildDAGWithRegPressure();
@@ -237,8 +235,8 @@ void VLIWMachineScheduler::schedule() {
placeDebugValues();
DEBUG({
- unsigned BBNum = begin()->getParent()->getNumber();
- dbgs() << "*** Final schedule for BB#" << BBNum << " ***\n";
+ dbgs() << "*** Final schedule for "
+ << printMBBReference(*begin()->getParent()) << " ***\n";
dumpSchedule();
dbgs() << '\n';
});
diff --git a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
index f42b6ed9935..d97ed4812f2 100644
--- a/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonOptAddrMode.cpp
@@ -461,7 +461,7 @@ bool HexagonOptAddrMode::changeAddAsl(NodeAddr<UseNode *> AddAslUN,
DEBUG(dbgs() << "[InstrNode]: " << Print<NodeAddr<InstrNode *>>(UseIA, *DFG)
<< "\n");
MachineInstr *UseMI = UseIA.Addr->getCode();
- DEBUG(dbgs() << "[MI <BB#" << UseMI->getParent()->getNumber()
+ DEBUG(dbgs() << "[MI <" << printMBBReference(*UseMI->getParent())
<< ">]: " << *UseMI << "\n");
const MCInstrDesc &UseMID = UseMI->getDesc();
assert(HII->getAddrMode(*UseMI) == HexagonII::BaseImmOffset);
@@ -570,7 +570,7 @@ bool HexagonOptAddrMode::processBlock(NodeAddr<BlockNode *> BA) {
NodeAddr<StmtNode *> OwnerN = UseN.Addr->getOwner(*DFG);
MachineInstr *UseMI = OwnerN.Addr->getCode();
- DEBUG(dbgs() << "\t\t[MI <BB#" << UseMI->getParent()->getNumber()
+ DEBUG(dbgs() << "\t\t[MI <" << printMBBReference(*UseMI->getParent())
<< ">]: " << *UseMI << "\n");
int UseMOnum = -1;
diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
index 354bb95e448..7f82a5c4c4d 100644
--- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
@@ -20,19 +20,18 @@
// ...
// %16<def> = NOT_p %15<kill>
// ...
-// JMP_c %16<kill>, <BB#1>, %pc<imp-def,dead>
+// JMP_c %16<kill>, <%bb.1>, %pc<imp-def,dead>
//
// Into
// %15<def> = CMPGTrr %6, %2;
// ...
-// JMP_cNot %15<kill>, <BB#1>, %pc<imp-def,dead>;
+// JMP_cNot %15<kill>, <%bb.1>, %pc<imp-def,dead>;
//
// Note: The peephole pass makes the instrucstions like
// %170<def> = SXTW %166 or %16<def> = NOT_p %15<kill>
// redundant and relies on some form of dead removal instructions, like
// DCE or DIE to actually eliminate them.
-
//===----------------------------------------------------------------------===//
#include "Hexagon.h"
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index 75d6750322b..68b5ddd4438 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -536,7 +536,7 @@ void HexagonSplitDoubleRegs::collectIndRegsForLoop(const MachineLoop *L,
Rs.insert(CmpR2);
DEBUG({
- dbgs() << "For loop at BB#" << HB->getNumber() << " ind regs: ";
+ dbgs() << "For loop at " << printMBBReference(*HB) << " ind regs: ";
dump_partition(dbgs(), Rs, *TRI);
dbgs() << '\n';
});
diff --git a/llvm/lib/Target/Hexagon/RDFGraph.cpp b/llvm/lib/Target/Hexagon/RDFGraph.cpp
index 50ebcd5302c..8513ebd1c76 100644
--- a/llvm/lib/Target/Hexagon/RDFGraph.cpp
+++ b/llvm/lib/Target/Hexagon/RDFGraph.cpp
@@ -247,7 +247,7 @@ raw_ostream &operator<< (raw_ostream &OS,
if (T != MI.operands_end()) {
OS << ' ';
if (T->isMBB())
- OS << "BB#" << T->getMBB()->getNumber();
+ OS << printMBBReference(*T->getMBB());
else if (T->isGlobal())
OS << T->getGlobal()->getName();
else if (T->isSymbol())
@@ -284,13 +284,13 @@ raw_ostream &operator<< (raw_ostream &OS,
auto PrintBBs = [&OS] (std::vector<int> Ns) -> void {
unsigned N = Ns.size();
for (int I : Ns) {
- OS << "BB#" << I;
+ OS << "%bb." << I;
if (--N)
OS << ", ";
}
};
- OS << Print<NodeId>(P.Obj.Id, P.G) << ": --- BB#" << BB->getNumber()
+ OS << Print<NodeId>(P.Obj.Id, P.G) << ": --- " << printMBBReference(*BB)
<< " --- preds(" << NP << "): ";
for (MachineBasicBlock *B : BB->predecessors())
Ns.push_back(B->getNumber());
@@ -1123,8 +1123,8 @@ void DataFlowGraph::pushDefs(NodeAddr<InstrNode*> IA, DefStackMap &DefM) {
if (!Defined.insert(RR.Reg).second) {
MachineInstr *MI = NodeAddr<StmtNode*>(IA).Addr->getCode();
dbgs() << "Multiple definitions of register: "
- << Print<RegisterRef>(RR, *this) << " in\n " << *MI
- << "in BB#" << MI->getParent()->getNumber() << '\n';
+ << Print<RegisterRef>(RR, *this) << " in\n " << *MI << "in "
+ << printMBBReference(*MI->getParent()) << '\n';
llvm_unreachable(nullptr);
}
#endif
diff --git a/llvm/lib/Target/Hexagon/RDFGraph.h b/llvm/lib/Target/Hexagon/RDFGraph.h
index 399b401c5ff..25c4b67230a 100644
--- a/llvm/lib/Target/Hexagon/RDFGraph.h
+++ b/llvm/lib/Target/Hexagon/RDFGraph.h
@@ -111,7 +111,7 @@
//
// DFG dump:[
// f1: Function foo
-// b2: === BB#0 === preds(0), succs(0):
+// b2: === %bb.0 === preds(0), succs(0):
// p3: phi [d4<r0>(,d12,u9):]
// p5: phi [d6<r1>(,,u10):]
// s7: add [d8<r2>(,,u13):, u9<r0>(d4):, u10<r1>(d6):]
diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
index 740cd11136b..13d9a174197 100644
--- a/llvm/lib/Target/Hexagon/RDFLiveness.cpp
+++ b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
@@ -814,7 +814,7 @@ void Liveness::computeLiveIns() {
for (auto I = B.livein_begin(), E = B.livein_end(); I != E; ++I)
LV.push_back(RegisterRef(I->PhysReg, I->LaneMask));
std::sort(LV.begin(), LV.end());
- dbgs() << "BB#" << B.getNumber() << "\t rec = {";
+ dbgs() << printMBBReference(B) << "\t rec = {";
for (auto I : LV)
dbgs() << ' ' << Print<RegisterRef>(I, DFG);
dbgs() << " }\n";
@@ -963,7 +963,7 @@ void Liveness::traverse(MachineBasicBlock *B, RefMap &LiveIn) {
}
if (Trace) {
- dbgs() << "\n-- BB#" << B->getNumber() << ": " << __func__
+ dbgs() << "\n-- " << printMBBReference(*B) << ": " << __func__
<< " after recursion into: {";
for (auto I : *N)
dbgs() << ' ' << I->getBlock()->getNumber();
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