1 files changed, 27 insertions, 19 deletions

diff --git a/llvm/lib/Target/Hexagon/RDFRegisters.cpp b/llvm/lib/Target/Hexagon/RDFRegisters.cpp
index fc5ad0aedb1..74d6ba53be7 100644
--- a/llvm/lib/Target/Hexagon/RDFRegisters.cpp
+++ b/llvm/lib/Target/Hexagon/RDFRegisters.cpp
@@ -49,6 +49,21 @@ PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
           RegMasks.insert(Op.getRegMask());
 }
 
+RegisterRef PhysicalRegisterInfo::normalize(RegisterRef RR) const {
+  if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
+    return RR;
+  const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass;
+  LaneBitmask RCMask = RC != nullptr ? RC->LaneMask : LaneBitmask(0x00000001);
+  LaneBitmask Common = RR.Mask & RCMask;
+
+  RegisterId SuperReg = RegInfos[RR.Reg].MaxSuper;
+// Ex: IP/EIP/RIP
+//  assert(RC != nullptr || RR.Reg == SuperReg);
+  uint32_t Sub = TRI.getSubRegIndex(SuperReg, RR.Reg);
+  LaneBitmask SuperMask = TRI.composeSubRegIndexLaneMask(Sub, Common);
+  return RegisterRef(SuperReg, SuperMask);
+}
+
 std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
   // Do not include RR in the alias set.
   std::set<RegisterId> AS;
@@ -73,6 +88,14 @@ std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
 bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const {
   assert(TargetRegisterInfo::isPhysicalRegister(RA.Reg));
   assert(TargetRegisterInfo::isPhysicalRegister(RB.Reg));
+
+  RegisterRef NA = normalize(RA);
+  RegisterRef NB = normalize(RB);
+  if (NA.Reg == NB.Reg)
+    return (NA.Mask & NB.Mask).any();
+
+  // The code below relies on the fact that RA and RB do not share a common
+  // super-register.
   MCRegUnitMaskIterator UMA(RA.Reg, &TRI);
   MCRegUnitMaskIterator UMB(RB.Reg, &TRI);
   // Reg units are returned in the numerical order.
@@ -186,21 +209,6 @@ bool PhysicalRegisterInfo::aliasMM(RegisterRef RM, RegisterRef RN) const {
 }
 
 
-RegisterRef RegisterAggr::normalize(RegisterRef RR) const {
-  if (PhysicalRegisterInfo::isRegMaskId(RR.Reg))
-    return RR;
-  const TargetRegisterClass *RC = PRI.RegInfos[RR.Reg].RegClass;
-  LaneBitmask RCMask = RC != nullptr ? RC->LaneMask : LaneBitmask(0x00000001);
-  LaneBitmask Common = RR.Mask & RCMask;
-
-  RegisterId SuperReg = PRI.RegInfos[RR.Reg].MaxSuper;
-// Ex: IP/EIP/RIP
-//  assert(RC != nullptr || RR.Reg == SuperReg);
-  uint32_t Sub = PRI.getTRI().getSubRegIndex(SuperReg, RR.Reg);
-  LaneBitmask SuperMask = PRI.getTRI().composeSubRegIndexLaneMask(Sub, Common);
-  return RegisterRef(SuperReg, SuperMask);
-}
-
 bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
   if (PhysicalRegisterInfo::isRegMaskId(RR.Reg)) {
     // XXX SLOW
@@ -213,7 +221,7 @@ bool RegisterAggr::hasAliasOf(RegisterRef RR) const {
     }
   }
 
-  RegisterRef NR = normalize(RR);
+  RegisterRef NR = PRI.normalize(RR);
   auto F = Masks.find(NR.Reg);
   if (F != Masks.end()) {
     if ((F->second & NR.Mask).any())
@@ -241,7 +249,7 @@ bool RegisterAggr::hasCoverOf(RegisterRef RR) const {
   }
 
   // Always have a cover for empty lane mask.
-  RegisterRef NR = normalize(RR);
+  RegisterRef NR = PRI.normalize(RR);
   if (NR.Mask.none())
     return true;
   auto F = Masks.find(NR.Reg);
@@ -262,7 +270,7 @@ RegisterAggr &RegisterAggr::insert(RegisterRef RR) {
     return *this;
   }
 
-  RegisterRef NR = normalize(RR);
+  RegisterRef NR = PRI.normalize(RR);
   auto F = Masks.find(NR.Reg);
   if (F == Masks.end())
     Masks.insert({NR.Reg, NR.Mask});
@@ -301,7 +309,7 @@ RegisterAggr &RegisterAggr::clear(RegisterRef RR) {
     return *this;
   }
 
-  RegisterRef NR = normalize(RR);
+  RegisterRef NR = PRI.normalize(RR);
   auto F = Masks.find(NR.Reg);
   if (F == Masks.end())
     return *this;