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-rw-r--r--llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp3
-rw-r--r--llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h2
-rw-r--r--llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp2
-rw-r--r--llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp4
4 files changed, 5 insertions, 6 deletions
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
index c140bd1d7ee..3bc238e84e2 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp
@@ -524,8 +524,7 @@ public:
bool Relaxable = false;
// Branches and loop-setup insns are handled as necessary by relaxation.
if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
- (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) ==
- HexagonII::TypeCOMPOUND &&
+ (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCJ &&
MCID.isBranch()) ||
(llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV &&
MCID.isBranch()) ||
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
index 4292f6b3faa..b4c35fd68b2 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonBaseInfo.h
@@ -44,7 +44,7 @@ namespace HexagonII {
TypeV4LDST = 9,
TypeNV = 10,
TypeDUPLEX = 11,
- TypeCOMPOUND = 12,
+ TypeCJ = 12,
TypeCVI_FIRST = 13,
TypeCVI_VA = TypeCVI_FIRST,
TypeCVI_VA_DV = 14,
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
index 2645a17b9bd..cdabe8aa44c 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp
@@ -126,7 +126,7 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction(
" `" << HexagonMCInstrInfo::getName(MCII, HMB) << "'"
"\n");
- if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCOMPOUND) {
+ if (llvm::HexagonMCInstrInfo::getType(MCII, HMB) == HexagonII::TypeCJ) {
for (unsigned i = 0; i < HMB.getNumOperands(); ++i)
if (HMB.getOperand(i).isReg()) {
unsigned Reg =
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
index e627f026c8a..f975ecb1928 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp
@@ -438,7 +438,7 @@ bool HexagonMCInstrInfo::isCofMax1(MCInstrInfo const &MCII, MCInst const &MCI) {
bool HexagonMCInstrInfo::isCompound(MCInstrInfo const &MCII,
MCInst const &MCI) {
- return (getType(MCII, MCI) == HexagonII::TypeCOMPOUND);
+ return getType(MCII, MCI) == HexagonII::TypeCJ;
}
bool HexagonMCInstrInfo::isDblRegForSubInst(unsigned Reg) {
@@ -470,7 +470,7 @@ bool HexagonMCInstrInfo::isConstExtended(MCInstrInfo const &MCII,
return true;
// Branch insns are handled as necessary by relaxation.
if ((HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeJ) ||
- (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCOMPOUND &&
+ (HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeCJ &&
HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()) ||
(HexagonMCInstrInfo::getType(MCII, MCI) == HexagonII::TypeNV &&
HexagonMCInstrInfo::getDesc(MCII, MCI).isBranch()))
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