1 files changed, 73 insertions, 45 deletions

diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp
index 0f7a337ba61..c842b9b7cf3 100644
--- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp
+++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCInst.cpp
@@ -12,52 +12,68 @@
 //===----------------------------------------------------------------------===//
 
 #include "HexagonInstrInfo.h"
-#include "HexagonTargetMachine.h"
 #include "MCTargetDesc/HexagonBaseInfo.h"
 #include "MCTargetDesc/HexagonMCInst.h"
 #include "MCTargetDesc/HexagonMCTargetDesc.h"
-#include "llvm/Support/TargetRegistry.h"
 
 using namespace llvm;
 
-HexagonMCInst::HexagonMCInst(unsigned op)
-    : packetBegin(false), packetEnd(false),
-      MCID(llvm::TheHexagonTarget.createMCInstrInfo()->get(op)) {
-  assert(MCID.getSize() == 4 && "All instructions should be 32bit");
-  setOpcode(op);
+// Return the slots used by the insn.
+unsigned HexagonMCInst::getUnits(const HexagonTargetMachine* TM) const {
+  const HexagonInstrInfo *QII = TM->getSubtargetImpl()->getInstrInfo();
+  const InstrItineraryData *II =
+      TM->getSubtargetImpl()->getInstrItineraryData();
+  const InstrStage*
+    IS = II->beginStage(QII->get(this->getOpcode()).getSchedClass());
+
+  return (IS->getUnits());
 }
 
-bool HexagonMCInst::isPacketBegin() const { return packetBegin; }
-bool HexagonMCInst::isPacketEnd() const { return packetEnd; }
-void HexagonMCInst::setPacketEnd(bool Y) { packetEnd = Y; }
-void HexagonMCInst::setPacketBegin(bool Y) { packetBegin = Y; }
+// Return the Hexagon ISA class for the insn.
+unsigned HexagonMCInst::getType() const {
+  const uint64_t F = MCID->TSFlags;
 
-unsigned HexagonMCInst::getUnits(HexagonTargetMachine const &TM) const {
-  const HexagonInstrInfo *QII = TM.getSubtargetImpl()->getInstrInfo();
-  const InstrItineraryData *II = TM.getSubtargetImpl()->getInstrItineraryData();
-  const InstrStage *IS =
-      II->beginStage(QII->get(this->getOpcode()).getSchedClass());
+  return ((F >> HexagonII::TypePos) & HexagonII::TypeMask);
+}
 
-  return (IS->getUnits());
+// Return whether the insn is an actual insn.
+bool HexagonMCInst::isCanon() const {
+  return (!MCID->isPseudo() &&
+          !isPrefix() &&
+          getType() != HexagonII::TypeENDLOOP);
 }
 
+// Return whether the insn is a prefix.
+bool HexagonMCInst::isPrefix() const {
+  return (getType() == HexagonII::TypePREFIX);
+}
+
+// Return whether the insn is solo, i.e., cannot be in a packet.
+bool HexagonMCInst::isSolo() const {
+  const uint64_t F = MCID->TSFlags;
+  return ((F >> HexagonII::SoloPos) & HexagonII::SoloMask);
+}
+
+// Return whether the insn is a new-value consumer.
 bool HexagonMCInst::isNewValue() const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = MCID->TSFlags;
   return ((F >> HexagonII::NewValuePos) & HexagonII::NewValueMask);
 }
 
+// Return whether the instruction is a legal new-value producer.
 bool HexagonMCInst::hasNewValue() const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = MCID->TSFlags;
   return ((F >> HexagonII::hasNewValuePos) & HexagonII::hasNewValueMask);
 }
 
-MCOperand const &HexagonMCInst::getNewValue() const {
-  const uint64_t F = MCID.TSFlags;
-  const unsigned O =
-      (F >> HexagonII::NewValueOpPos) & HexagonII::NewValueOpMask;
-  const MCOperand &MCO = getOperand(O);
+// Return the operand that consumes or produces a new value.
+const MCOperand& HexagonMCInst::getNewValue() const {
+  const uint64_t F = MCID->TSFlags;
+  const unsigned O = (F >> HexagonII::NewValueOpPos) &
+                     HexagonII::NewValueOpMask;
+  const MCOperand& MCO = getOperand(O);
 
-  assert((isNewValue() || hasNewValue()) && MCO.isReg());
+  assert ((isNewValue() || hasNewValue()) && MCO.isReg());
   return (MCO);
 }
 
@@ -68,6 +84,7 @@ MCOperand const &HexagonMCInst::getNewValue() const {
 // 2) For immediate extended operands, return true only if the value is
 //    out-of-range.
 // 3) For global address, always return true.
+
 bool HexagonMCInst::isConstExtended(void) const {
   if (isExtended())
     return true;
@@ -76,9 +93,9 @@ bool HexagonMCInst::isConstExtended(void) const {
     return false;
 
   short ExtOpNum = getCExtOpNum();
-  int MinValue = getMinValue();
-  int MaxValue = getMaxValue();
-  const MCOperand &MO = getOperand(ExtOpNum);
+  int MinValue   = getMinValue();
+  int MaxValue   = getMaxValue();
+  const MCOperand& MO = getOperand(ExtOpNum);
 
   // We could be using an instruction with an extendable immediate and shoehorn
   // a global address into it. If it is a global address it will be constant
@@ -97,51 +114,62 @@ bool HexagonMCInst::isConstExtended(void) const {
   return (ImmValue < MinValue || ImmValue > MaxValue);
 }
 
+// Return whether the instruction must be always extended.
 bool HexagonMCInst::isExtended(void) const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = MCID->TSFlags;
   return (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
 }
 
+// Return true if the instruction may be extended based on the operand value.
 bool HexagonMCInst::isExtendable(void) const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = MCID->TSFlags;
   return (F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask;
 }
 
+// Return number of bits in the constant extended operand.
 unsigned HexagonMCInst::getBitCount(void) const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = MCID->TSFlags;
   return ((F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask);
 }
 
+// Return constant extended operand number.
 unsigned short HexagonMCInst::getCExtOpNum(void) const {
-  const uint64_t F = MCID.TSFlags;
+  const uint64_t F = MCID->TSFlags;
   return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
 }
 
+// Return whether the operand can be constant extended.
 bool HexagonMCInst::isOperandExtended(const unsigned short OperandNum) const {
-  const uint64_t F = MCID.TSFlags;
-  return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask) ==
-         OperandNum;
+  const uint64_t F = MCID->TSFlags;
+  return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
+          == OperandNum;
 }
 
+// Return the min value that a constant extendable operand can have
+// without being extended.
 int HexagonMCInst::getMinValue(void) const {
-  const uint64_t F = MCID.TSFlags;
-  unsigned isSigned =
-      (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
-  unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
+  const uint64_t F = MCID->TSFlags;
+  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
+                    & HexagonII::ExtentSignedMask;
+  unsigned bits =  (F >> HexagonII::ExtentBitsPos)
+                    & HexagonII::ExtentBitsMask;
 
-  if (isSigned)
+  if (isSigned) // if value is signed
     return -1U << (bits - 1);
   else
     return 0;
 }
 
+// Return the max value that a constant extendable operand can have
+// without being extended.
 int HexagonMCInst::getMaxValue(void) const {
-  const uint64_t F = MCID.TSFlags;
-  unsigned isSigned =
-      (F >> HexagonII::ExtentSignedPos) & HexagonII::ExtentSignedMask;
-  unsigned bits = (F >> HexagonII::ExtentBitsPos) & HexagonII::ExtentBitsMask;
+  const uint64_t F = MCID->TSFlags;
+  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
+                    & HexagonII::ExtentSignedMask;
+  unsigned bits =  (F >> HexagonII::ExtentBitsPos)
+                    & HexagonII::ExtentBitsMask;
 
-  if (isSigned)
+  if (isSigned) // if value is signed
     return ~(-1U << (bits - 1));
   else
     return ~(-1U << bits);