diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp | 81 |
1 files changed, 43 insertions, 38 deletions
diff --git a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp index 32021eee3d1..4c2fc988048 100644 --- a/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp +++ b/llvm/lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp @@ -1,4 +1,4 @@ -//===-- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions ------------===// +//===- HexagonMCCodeEmitter.cpp - Hexagon Target Descriptions -------------===// // // The LLVM Compiler Infrastructure // @@ -11,19 +11,29 @@ #include "Hexagon.h" #include "MCTargetDesc/HexagonBaseInfo.h" #include "MCTargetDesc/HexagonFixupKinds.h" +#include "MCTargetDesc/HexagonMCExpr.h" #include "MCTargetDesc/HexagonMCInstrInfo.h" #include "MCTargetDesc/HexagonMCTargetDesc.h" #include "llvm/ADT/Statistic.h" -#include "llvm/MC/MCCodeEmitter.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCExpr.h" +#include "llvm/MC/MCFixup.h" #include "llvm/MC/MCInst.h" +#include "llvm/MC/MCInstrDesc.h" #include "llvm/MC/MCInstrInfo.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/Compiler.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/Endian.h" #include "llvm/Support/EndianStream.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/raw_ostream.h" +#include <cassert> +#include <cstddef> +#include <cstdint> +#include <string> #define DEBUG_TYPE "mccodeemitter" @@ -89,7 +99,6 @@ void HexagonMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS, *Addend += HEXAGON_INSTR_SIZE; ++*CurrentIndex; } - return; } static bool RegisterMatches(unsigned Consumer, unsigned Producer, @@ -158,18 +167,16 @@ void HexagonMCCodeEmitter::EncodeSingleInstruction( ++MCNumEmitted; } -namespace { LLVM_ATTRIBUTE_NORETURN -void raise_relocation_error(unsigned bits, unsigned kind) { +static void raise_relocation_error(unsigned bits, unsigned kind) { std::string Text; { - llvm::raw_string_ostream Stream(Text); + raw_string_ostream Stream(Text); Stream << "Unrecognized relocation combination bits: " << bits << " kind: " << kind; } report_fatal_error(Text); } -} /// getFixupNoBits - Some insns are not extended and thus have no /// bits. These cases require a more brute force method for determining @@ -178,7 +185,7 @@ Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits( MCInstrInfo const &MCII, const MCInst &MI, const MCOperand &MO, const MCSymbolRefExpr::VariantKind kind) const { const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(MCII, MI); - unsigned insnType = llvm::HexagonMCInstrInfo::getType(MCII, MI); + unsigned insnType = HexagonMCInstrInfo::getType(MCII, MI); if (insnType == HexagonII::TypeEXTENDER) { switch (kind) { @@ -303,34 +310,34 @@ Hexagon::Fixups HexagonMCCodeEmitter::getFixupNoBits( } namespace llvm { + extern const MCInstrDesc HexagonInsts[]; -} -namespace { - bool isPCRel (unsigned Kind) { - switch(Kind){ - case fixup_Hexagon_B22_PCREL: - case fixup_Hexagon_B15_PCREL: - case fixup_Hexagon_B7_PCREL: - case fixup_Hexagon_B13_PCREL: - case fixup_Hexagon_B9_PCREL: - case fixup_Hexagon_B32_PCREL_X: - case fixup_Hexagon_B22_PCREL_X: - case fixup_Hexagon_B15_PCREL_X: - case fixup_Hexagon_B13_PCREL_X: - case fixup_Hexagon_B9_PCREL_X: - case fixup_Hexagon_B7_PCREL_X: - case fixup_Hexagon_32_PCREL: - case fixup_Hexagon_PLT_B22_PCREL: - case fixup_Hexagon_GD_PLT_B22_PCREL: - case fixup_Hexagon_LD_PLT_B22_PCREL: - case fixup_Hexagon_GD_PLT_B22_PCREL_X: - case fixup_Hexagon_LD_PLT_B22_PCREL_X: - case fixup_Hexagon_6_PCREL_X: - return true; - default: - return false; - } +} // end namespace llvm + +static bool isPCRel (unsigned Kind) { + switch(Kind){ + case fixup_Hexagon_B22_PCREL: + case fixup_Hexagon_B15_PCREL: + case fixup_Hexagon_B7_PCREL: + case fixup_Hexagon_B13_PCREL: + case fixup_Hexagon_B9_PCREL: + case fixup_Hexagon_B32_PCREL_X: + case fixup_Hexagon_B22_PCREL_X: + case fixup_Hexagon_B15_PCREL_X: + case fixup_Hexagon_B13_PCREL_X: + case fixup_Hexagon_B9_PCREL_X: + case fixup_Hexagon_B7_PCREL_X: + case fixup_Hexagon_32_PCREL: + case fixup_Hexagon_PLT_B22_PCREL: + case fixup_Hexagon_GD_PLT_B22_PCREL: + case fixup_Hexagon_LD_PLT_B22_PCREL: + case fixup_Hexagon_GD_PLT_B22_PCREL_X: + case fixup_Hexagon_LD_PLT_B22_PCREL_X: + case fixup_Hexagon_6_PCREL_X: + return true; + default: + return false; } } @@ -339,7 +346,6 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, const MCExpr *ME, SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const - { if (isa<HexagonMCExpr>(ME)) ME = &HexagonMCInstrInfo::getExpr(*ME); @@ -476,7 +482,7 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, } } else switch (kind) { - case MCSymbolRefExpr::VK_None: { + case MCSymbolRefExpr::VK_None: if (HexagonMCInstrInfo::s27_2_reloc(*MO.getExpr())) FixupKind = Hexagon::fixup_Hexagon_27_REG; else @@ -505,7 +511,6 @@ unsigned HexagonMCCodeEmitter::getExprOpValue(const MCInst &MI, } else raise_relocation_error(bits, kind); break; - } case MCSymbolRefExpr::VK_DTPREL: FixupKind = Hexagon::fixup_Hexagon_DTPREL_16; break; @@ -787,7 +792,7 @@ HexagonMCCodeEmitter::getMachineOpValue(MCInst const &MI, MCOperand const &MO, if (MO.isReg()) { unsigned Reg = MO.getReg(); if (HexagonMCInstrInfo::isSubInstruction(MI) || - llvm::HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ) + HexagonMCInstrInfo::getType(MCII, MI) == HexagonII::TypeCJ) return HexagonMCInstrInfo::getDuplexRegisterNumbering(Reg); return MCT.getRegisterInfo()->getEncodingValue(Reg); } |
