diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonSubtarget.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 7596bb5a435..37f1e455b23 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -92,7 +92,7 @@ static cl::opt<bool> EnableCheckBankConflict("hexagon-check-bank-conflict", HexagonSubtarget::HexagonSubtarget(const Triple &TT, StringRef CPU, StringRef FS, const TargetMachine &TM) - : HexagonGenSubtargetInfo(TT, CPU, FS), + : HexagonGenSubtargetInfo(TT, CPU, FS), OptLevel(TM.getOptLevel()), CPUString(Hexagon_MC::selectHexagonCPU(TT, CPU)), InstrInfo(initializeSubtargetDependencies(CPU, FS)), RegInfo(getHwMode()), TLInfo(TM, *this), @@ -294,6 +294,14 @@ void HexagonSubtarget::BankConflictMutation::apply(ScheduleDAGInstrs *DAG) { } } +/// \brief Enable use of alias analysis during code generation (during MI +/// scheduling, DAGCombine, etc.). +bool HexagonSubtarget::useAA() const { + if (OptLevel != CodeGenOpt::None) + return true; + return false; +} + /// \brief Perform target specific adjustments to the latency of a schedule /// dependency. void HexagonSubtarget::adjustSchedDependency(SUnit *Src, SUnit *Dst, |
