diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonSubtarget.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonSubtarget.cpp | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp index 7eed2898f61..7596bb5a435 100644 --- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp +++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp @@ -223,8 +223,8 @@ void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAG) { // both the return value and the argument for the next call being in %r0. // Example: // 1: <call1> - // 2: %vregX = COPY %r0 - // 3: <use of %vregX> + // 2: %vreg = COPY %r0 + // 3: <use of %vreg> // 4: %r0 = ... // 5: <call2> // The scheduler would often swap 3 and 4, so an additional register is @@ -234,12 +234,12 @@ void HexagonSubtarget::CallMutation::apply(ScheduleDAGInstrs *DAG) { const MachineInstr *MI = DAG->SUnits[su].getInstr(); if (MI->isCopy() && (MI->readsRegister(Hexagon::R0, &TRI) || MI->readsRegister(Hexagon::V0, &TRI))) { - // %vregX = COPY %r0 + // %vreg = COPY %r0 VRegHoldingRet = MI->getOperand(0).getReg(); RetRegister = MI->getOperand(1).getReg(); LastUseOfRet = nullptr; } else if (VRegHoldingRet && MI->readsVirtualRegister(VRegHoldingRet)) - // <use of %vregX> + // <use of %X> LastUseOfRet = &DAG->SUnits[su]; else if (LastUseOfRet && MI->definesRegister(RetRegister, &TRI)) // %r0 = ... |
