1 files changed, 4 insertions, 4 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
index cc85a995d40..27b3fb72a20 100644
--- a/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonRegisterInfo.cpp
@@ -256,13 +256,13 @@ unsigned HexagonRegisterInfo::getStackRegister() const {
 
 
 unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
-      const TargetRegisterClass *RC, unsigned GenIdx) const {
+      const TargetRegisterClass &RC, unsigned GenIdx) const {
   assert(GenIdx == Hexagon::ps_sub_lo || GenIdx == Hexagon::ps_sub_hi);
 
   static const unsigned ISub[] = { Hexagon::isub_lo, Hexagon::isub_hi };
   static const unsigned VSub[] = { Hexagon::vsub_lo, Hexagon::vsub_hi };
 
-  switch (RC->getID()) {
+  switch (RC.getID()) {
     case Hexagon::CtrRegs64RegClassID:
     case Hexagon::DoubleRegsRegClassID:
       return ISub[GenIdx];
@@ -270,8 +270,8 @@ unsigned HexagonRegisterInfo::getHexagonSubRegIndex(
       return VSub[GenIdx];
   }
 
-  if (const TargetRegisterClass *SuperRC = *RC->getSuperClasses())
-    return getHexagonSubRegIndex(SuperRC, GenIdx);
+  if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
+    return getHexagonSubRegIndex(*SuperRC, GenIdx);
 
   llvm_unreachable("Invalid register class");
 }