diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp | 64 |
1 files changed, 32 insertions, 32 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp index 977e2aea066..c7ca82cf897 100644 --- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp +++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp @@ -1470,12 +1470,13 @@ bool HexagonFrameLowering::expandStoreInt(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { MachineInstr *MI = &*It; + if (!MI->getOperand(0).isFI()) + return false; + DebugLoc DL = MI->getDebugLoc(); unsigned Opc = MI->getOpcode(); unsigned SrcR = MI->getOperand(2).getReg(); bool IsKill = MI->getOperand(2).isKill(); - - assert(MI->getOperand(0).isFI() && "Expect a frame index"); int FI = MI->getOperand(0).getIndex(); // TmpR = C2_tfrpr SrcR if SrcR is a predicate register @@ -1502,11 +1503,12 @@ bool HexagonFrameLowering::expandLoadInt(MachineBasicBlock &B, MachineBasicBlock::iterator It, MachineRegisterInfo &MRI, const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { MachineInstr *MI = &*It; + if (!MI->getOperand(1).isFI()) + return false; + DebugLoc DL = MI->getDebugLoc(); unsigned Opc = MI->getOpcode(); unsigned DstR = MI->getOperand(0).getReg(); - - assert(MI->getOperand(1).isFI() && "Expect a frame index"); int FI = MI->getOperand(1).getIndex(); // TmpR = L2_loadri_io FI, 0 @@ -1534,11 +1536,12 @@ bool HexagonFrameLowering::expandStoreVecPred(MachineBasicBlock &B, const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { auto &HST = B.getParent()->getSubtarget<HexagonSubtarget>(); MachineInstr *MI = &*It; + if (!MI->getOperand(0).isFI()) + return false; + DebugLoc DL = MI->getDebugLoc(); unsigned SrcR = MI->getOperand(2).getReg(); bool IsKill = MI->getOperand(2).isKill(); - - assert(MI->getOperand(0).isFI() && "Expect a frame index"); int FI = MI->getOperand(0).getIndex(); bool Is128B = HST.useHVXDblOps(); @@ -1575,10 +1578,11 @@ bool HexagonFrameLowering::expandLoadVecPred(MachineBasicBlock &B, const HexagonInstrInfo &HII, SmallVectorImpl<unsigned> &NewRegs) const { auto &HST = B.getParent()->getSubtarget<HexagonSubtarget>(); MachineInstr *MI = &*It; + if (!MI->getOperand(1).isFI()) + return false; + DebugLoc DL = MI->getDebugLoc(); unsigned DstR = MI->getOperand(0).getReg(); - - assert(MI->getOperand(1).isFI() && "Expect a frame index"); int FI = MI->getOperand(1).getIndex(); bool Is128B = HST.useHVXDblOps(); @@ -1616,14 +1620,14 @@ bool HexagonFrameLowering::expandStoreVec2(MachineBasicBlock &B, auto &MFI = MF.getFrameInfo(); auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); MachineInstr *MI = &*It; - DebugLoc DL = MI->getDebugLoc(); + if (!MI->getOperand(0).isFI()) + return false; + DebugLoc DL = MI->getDebugLoc(); unsigned SrcR = MI->getOperand(2).getReg(); unsigned SrcLo = HRI.getSubReg(SrcR, Hexagon::subreg_loreg); unsigned SrcHi = HRI.getSubReg(SrcR, Hexagon::subreg_hireg); bool IsKill = MI->getOperand(2).isKill(); - - assert(MI->getOperand(0).isFI() && "Expect a frame index"); int FI = MI->getOperand(0).getIndex(); bool Is128B = HST.useHVXDblOps(); @@ -1670,13 +1674,13 @@ bool HexagonFrameLowering::expandLoadVec2(MachineBasicBlock &B, auto &MFI = MF.getFrameInfo(); auto &HRI = *MF.getSubtarget<HexagonSubtarget>().getRegisterInfo(); MachineInstr *MI = &*It; - DebugLoc DL = MI->getDebugLoc(); + if (!MI->getOperand(1).isFI()) + return false; + DebugLoc DL = MI->getDebugLoc(); unsigned DstR = MI->getOperand(0).getReg(); unsigned DstHi = HRI.getSubReg(DstR, Hexagon::subreg_hireg); unsigned DstLo = HRI.getSubReg(DstR, Hexagon::subreg_loreg); - - assert(MI->getOperand(1).isFI() && "Expect a frame index"); int FI = MI->getOperand(1).getIndex(); bool Is128B = HST.useHVXDblOps(); @@ -1720,12 +1724,12 @@ bool HexagonFrameLowering::expandStoreVec(MachineBasicBlock &B, auto &HST = MF.getSubtarget<HexagonSubtarget>(); auto &MFI = MF.getFrameInfo(); MachineInstr *MI = &*It; - DebugLoc DL = MI->getDebugLoc(); + if (!MI->getOperand(0).isFI()) + return false; + DebugLoc DL = MI->getDebugLoc(); unsigned SrcR = MI->getOperand(2).getReg(); bool IsKill = MI->getOperand(2).isKill(); - - assert(MI->getOperand(0).isFI() && "Expect a frame index"); int FI = MI->getOperand(0).getIndex(); bool Is128B = HST.useHVXDblOps(); @@ -1758,11 +1762,11 @@ bool HexagonFrameLowering::expandLoadVec(MachineBasicBlock &B, auto &HST = MF.getSubtarget<HexagonSubtarget>(); auto &MFI = MF.getFrameInfo(); MachineInstr *MI = &*It; - DebugLoc DL = MI->getDebugLoc(); + if (!MI->getOperand(1).isFI()) + return false; + DebugLoc DL = MI->getDebugLoc(); unsigned DstR = MI->getOperand(0).getReg(); - - assert(MI->getOperand(1).isFI() && "Expect a frame index"); int FI = MI->getOperand(1).getIndex(); bool Is128B = HST.useHVXDblOps(); @@ -1823,22 +1827,18 @@ bool HexagonFrameLowering::expandSpillMacros(MachineFunction &MF, case Hexagon::LDriq_pred_V6_128B: Changed |= expandLoadVecPred(B, I, MRI, HII, NewRegs); break; - case Hexagon::LDrivv_pseudo_V6: - case Hexagon::LDrivv_pseudo_V6_128B: + case Hexagon::PS_vloadrw_ai: + case Hexagon::PS_vloadrwu_ai: + case Hexagon::PS_vloadrw_ai_128B: + case Hexagon::PS_vloadrwu_ai_128B: Changed |= expandLoadVec2(B, I, MRI, HII, NewRegs); break; - case Hexagon::STrivv_pseudo_V6: - case Hexagon::STrivv_pseudo_V6_128B: + case Hexagon::PS_vstorerw_ai: + case Hexagon::PS_vstorerwu_ai: + case Hexagon::PS_vstorerw_ai_128B: + case Hexagon::PS_vstorerwu_ai_128B: Changed |= expandStoreVec2(B, I, MRI, HII, NewRegs); break; - case Hexagon::STriv_pseudo_V6: - case Hexagon::STriv_pseudo_V6_128B: - Changed |= expandStoreVec(B, I, MRI, HII, NewRegs); - break; - case Hexagon::LDriv_pseudo_V6: - case Hexagon::LDriv_pseudo_V6_128B: - Changed |= expandLoadVec(B, I, MRI, HII, NewRegs); - break; } } } |
