1 files changed, 11 insertions, 15 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index 5f375f8dc74..36080997ec6 100644
--- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -440,21 +440,17 @@ HexagonCopyToCombine::findPotentialNewifiableTFRs(MachineBasicBlock &BB) {
 
     // Put instructions that last defined integer or double registers into the
     // map.
-    for (MachineOperand &Op : MI.operands()) {
-      if (Op.isReg()) {
-        if (!Op.isDef() || !Op.getReg())
-          continue;
-        unsigned Reg = Op.getReg();
-        if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
-          for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
-            LastDef[*SubRegs] = &MI;
-        } else if (Hexagon::IntRegsRegClass.contains(Reg))
-          LastDef[Reg] = &MI;
-      } else if (Op.isRegMask()) {
-        for (unsigned Reg : Hexagon::IntRegsRegClass)
-          if (Op.clobbersPhysReg(Reg))
-            LastDef[Reg] = &MI;
-      }
+    for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
+      MachineOperand &Op = MI.getOperand(I);
+      if (!Op.isReg() || !Op.isDef() || !Op.getReg())
+        continue;
+      unsigned Reg = Op.getReg();
+      if (Hexagon::DoubleRegsRegClass.contains(Reg)) {
+        for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
+          LastDef[*SubRegs] = &MI;
+        }
+      } else if (Hexagon::IntRegsRegClass.contains(Reg))
+        LastDef[Reg] = &MI;
     }
   }
 }