diff options
Diffstat (limited to 'llvm/lib/Target/Hexagon/HexagonBitTracker.cpp')
| -rw-r--r-- | llvm/lib/Target/Hexagon/HexagonBitTracker.cpp | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp index 610fc2598f8..ea438c6e462 100644 --- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp +++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp @@ -95,8 +95,8 @@ BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const { if (Sub == 0) return MachineEvaluator::mask(Reg, 0); - const TargetRegisterClass *RC = MRI.getRegClass(Reg); - unsigned ID = RC->getID(); + const TargetRegisterClass &RC = *MRI.getRegClass(Reg); + unsigned ID = RC.getID(); uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); auto &HRI = static_cast<const HexagonRegisterInfo&>(TRI); bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo)); @@ -109,7 +109,8 @@ BT::BitMask HexagonEvaluator::mask(unsigned Reg, unsigned Sub) const { break; } #ifndef NDEBUG - dbgs() << PrintReg(Reg, &TRI, Sub) << '\n'; + dbgs() << PrintReg(Reg, &TRI, Sub) << " in reg class " + << TRI.getRegClassName(&RC) << '\n'; #endif llvm_unreachable("Unexpected register/subregister"); } |
