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-rw-r--r--llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp33
1 files changed, 33 insertions, 0 deletions
diff --git a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
index 54db5ad4374..01ba1ccd37f 100644
--- a/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonAsmPrinter.cpp
@@ -282,6 +282,36 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
break;
}
+ case Hexagon::A2_tfrf: {
+ Inst.setOpcode(Hexagon::A2_paddif);
+ Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
+ break;
+ }
+
+ case Hexagon::A2_tfrt: {
+ Inst.setOpcode(Hexagon::A2_paddit);
+ Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
+ break;
+ }
+
+ case Hexagon::A2_tfrfnew: {
+ Inst.setOpcode(Hexagon::A2_paddifnew);
+ Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
+ break;
+ }
+
+ case Hexagon::A2_tfrtnew: {
+ Inst.setOpcode(Hexagon::A2_padditnew);
+ Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(0, OutContext)));
+ break;
+ }
+
+ case Hexagon::A2_zxtb: {
+ Inst.setOpcode(Hexagon::A2_andir);
+ Inst.addOperand(MCOperand::createExpr(MCConstantExpr::create(255, OutContext)));
+ break;
+ }
+
// "$dst = CONST64(#$src1)",
case Hexagon::CONST64:
if (!OutStreamer->hasRawTextSupport()) {
@@ -376,6 +406,9 @@ void HexagonAsmPrinter::HexagonProcessInstruction(MCInst &Inst,
Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
return;
}
+ case Hexagon::PS_call_nr:
+ Inst.setOpcode(Hexagon::J2_call);
+ break;
case Hexagon::S5_asrhub_rnd_sat_goodsyntax: {
MCOperand &MO = MappedInst.getOperand(2);
int64_t Imm;
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