1 files changed, 55 insertions, 22 deletions

diff --git a/llvm/lib/Target/Hexagon/Hexagon.td b/llvm/lib/Target/Hexagon/Hexagon.td
index 3218f2510e5..6292e2a7a4e 100644
--- a/llvm/lib/Target/Hexagon/Hexagon.td
+++ b/llvm/lib/Target/Hexagon/Hexagon.td
@@ -25,33 +25,36 @@ include "llvm/Target/Target.td"
 include "HexagonDepArch.td"
 
 // Hexagon ISA Extensions
-def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
+def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
       "Hexagon::ArchEnum::V60", "Hexagon HVX instructions">;
+def ExtensionHVXV60: SubtargetFeature<"hvxv60", "HexagonHVXVersion",
+      "Hexagon::ArchEnum::V60", "Hexagon HVX instructions",
+      [ExtensionHVX]>;
 def ExtensionHVXV62: SubtargetFeature<"hvxv62", "HexagonHVXVersion",
       "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
-      [ExtensionHVXV60]>;
-def ExtensionHVX: SubtargetFeature<"hvx", "HexagonHVXVersion",
-      "Hexagon::ArchEnum::V62", "Hexagon HVX instructions",
-      [ExtensionHVXV60,
-       ExtensionHVXV62]>;
+      [ExtensionHVX,ExtensionHVXV60]>;
+def ExtensionHVXV65: SubtargetFeature<"hvxv65", "HexagonHVXVersion",
+      "Hexagon::ArchEnum::V65", "Hexagon HVX instructions",
+      [ExtensionHVX,ExtensionHVXV60, ExtensionHVXV62]>;
 def ExtensionHVX64B
     : SubtargetFeature<"hvx-length64b", "UseHVX64BOps", "true",
-                       "Hexagon HVX 64B instructions",
-                        [ExtensionHVXV60, ExtensionHVXV62]>;
+                       "Hexagon HVX 64B instructions", [ExtensionHVX]>;
 def ExtensionHVX128B
     : SubtargetFeature<"hvx-length128b", "UseHVX128BOps", "true",
-                       "Hexagon HVX 128B instructions",
-                        [ExtensionHVXV60, ExtensionHVXV62]>;
+                       "Hexagon HVX 128B instructions", [ExtensionHVX]>;
 
 // This is an alias to ExtensionHVX128B to accept the hvx-double as
 // an acceptable subtarget feature.
 def ExtensionHVXDbl
     : SubtargetFeature<"hvx-double", "UseHVX128BOps", "true",
-                       "Hexagon HVX 128B instructions",
-                        [ExtensionHVXV60, ExtensionHVXV62]>;
+                       "Hexagon HVX 128B instructions", [ExtensionHVX128B]>;
 
 def FeatureLongCalls: SubtargetFeature<"long-calls", "UseLongCalls", "true",
       "Use constant-extended calls">;
+def FeatureMemNoShuf: SubtargetFeature<"mem_noshuf", "HasMemNoShuf", "false",
+      "Supports mem_noshuf feature">;
+def FeatureDuplex : SubtargetFeature<"duplex", "EnableDuplex", "true",
+      "Enable generation of duplex instruction">;
 
 //===----------------------------------------------------------------------===//
 // Hexagon Instruction Predicate Definitions.
@@ -69,6 +72,8 @@ def UseHVXV60          : Predicate<"HST->useHVXOps()">,
                          AssemblerPredicate<"ExtensionHVXV60">;
 def UseHVXV62          : Predicate<"HST->useHVXOps()">,
                          AssemblerPredicate<"ExtensionHVXV62">;
+def UseHVXV65          : Predicate<"HST->useHVXOps()">,
+                         AssemblerPredicate<"ExtensionHVXV65">;
 
 def Hvx64     : HwMode<"+hvx-length64b">;
 def Hvx64old  : HwMode<"-hvx-double">;
@@ -80,21 +85,22 @@ def Hvx128old : HwMode<"+hvx-double">;
 //===----------------------------------------------------------------------===//
 
 class ImmRegShl;
+// ImmRegRel - Filter class used to relate instructions having reg-reg form
+// with their reg-imm counterparts.
+class ImmRegRel;
 // PredRel - Filter class used to relate non-predicated instructions with their
 // predicated forms.
 class PredRel;
 // PredNewRel - Filter class used to relate predicated instructions with their
 // predicate-new forms.
 class PredNewRel: PredRel;
-// ImmRegRel - Filter class used to relate instructions having reg-reg form
-// with their reg-imm counterparts.
-class ImmRegRel;
 // NewValueRel - Filter class used to relate regular store instructions with
 // their new-value store form.
 class NewValueRel: PredNewRel;
 // NewValueRel - Filter class used to relate load/store instructions having
 // different addressing modes with each other.
 class AddrModeRel: NewValueRel;
+class PostInc_BaseImm;
 class IntrinsicsRel;
 
 //===----------------------------------------------------------------------===//
@@ -220,6 +226,22 @@ def changeAddrMode_rr_io: InstrMapping {
   let ValueCols = [["BaseImmOffset"]];
 }
 
+def changeAddrMode_pi_io: InstrMapping {
+  let FilterClass = "PostInc_BaseImm";
+  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
+  let ColFields = ["addrMode"];
+  let KeyCol = ["PostInc"];
+  let ValueCols = [["BaseImmOffset"]];
+}
+
+def changeAddrMode_io_pi: InstrMapping {
+  let FilterClass = "PostInc_BaseImm";
+  let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
+  let ColFields = ["addrMode"];
+  let KeyCol = ["BaseImmOffset"];
+  let ValueCols = [["PostInc"]];
+}
+
 def changeAddrMode_rr_ur: InstrMapping {
   let FilterClass = "ImmRegShl";
   let RowFields = ["CextOpcode", "PredSense", "PNewValue", "isNVStore"];
@@ -268,7 +290,7 @@ def getRealHWInstr : InstrMapping {
   let ValueCols = [["Pseudo"], ["Real"]];
 }
 //===----------------------------------------------------------------------===//
-// Register File, Calling Conv, Instruction Descriptions
+// Register File, Instruction Descriptions
 //===----------------------------------------------------------------------===//
 include "HexagonSchedule.td"
 include "HexagonRegisterInfo.td"
@@ -280,9 +302,11 @@ include "HexagonDepInstrFormats.td"
 include "HexagonDepInstrInfo.td"
 include "HexagonPseudo.td"
 include "HexagonPatterns.td"
+include "HexagonPatternsV65.td"
 include "HexagonDepMappings.td"
 include "HexagonIntrinsics.td"
 include "HexagonMapAsm2IntrinV62.gen.td"
+include "HexagonMapAsm2IntrinV65.gen.td"
 
 def HexagonInstrInfo : InstrInfo;
 
@@ -295,15 +319,18 @@ class Proc<string Name, SchedMachineModel Model,
  : ProcessorModel<Name, Model, Features>;
 
 def : Proc<"hexagonv4",  HexagonModelV4,
-           [ArchV4]>;
+           [ArchV4, FeatureDuplex]>;
 def : Proc<"hexagonv5",  HexagonModelV4,
-           [ArchV4, ArchV5]>;
+           [ArchV4, ArchV5, FeatureDuplex]>;
 def : Proc<"hexagonv55", HexagonModelV55,
-           [ArchV4, ArchV5, ArchV55]>;
+           [ArchV4, ArchV5, ArchV55, FeatureDuplex]>;
 def : Proc<"hexagonv60", HexagonModelV60,
-           [ArchV4, ArchV5, ArchV55, ArchV60]>;
+           [ArchV4, ArchV5, ArchV55, ArchV60, FeatureDuplex]>;
 def : Proc<"hexagonv62", HexagonModelV62,
-           [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62]>;
+           [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, FeatureDuplex]>;
+def : Proc<"hexagonv65", HexagonModelV65,
+           [ArchV4, ArchV5, ArchV55, ArchV60, ArchV62, ArchV65,
+            FeatureMemNoShuf, FeatureDuplex]>;
 
 //===----------------------------------------------------------------------===//
 // Declare the target which we are implementing
@@ -317,11 +344,17 @@ def HexagonAsmParser : AsmParser {
 def HexagonAsmParserVariant : AsmParserVariant {
   int Variant = 0;
   string TokenizingCharacters = "#()=:.<>!+*-|^&";
+  string BreakCharacters = "";
+}
+
+def HexagonAsmWriter : AsmWriter {
+  string AsmWriterClassName  = "InstPrinter";
+  bit isMCAsmWriter = 1;
 }
 
 def Hexagon : Target {
-  // Pull in Instruction Info:
   let InstructionSet = HexagonInstrInfo;
   let AssemblyParsers = [HexagonAsmParser];
   let AssemblyParserVariants = [HexagonAsmParserVariant];
+  let AssemblyWriters = [HexagonAsmWriter];
 }