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Diffstat (limited to 'llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp')
-rw-r--r--llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp238
1 files changed, 119 insertions, 119 deletions
diff --git a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index cca52883ffc..dd7009f2005 100644
--- a/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -103,11 +103,11 @@ namespace {
bool
isIntS16Immediate(ConstantSDNode *CN, short &Imm)
{
- MVT vt = CN->getValueType(0);
+ EVT vt = CN->getValueType(0);
Imm = (short) CN->getZExtValue();
- if (vt.getSimpleVT() >= MVT::i1 && vt.getSimpleVT() <= MVT::i16) {
+ if (vt.getSimpleVT() >= EVT::i1 && vt.getSimpleVT() <= EVT::i16) {
return true;
- } else if (vt == MVT::i32) {
+ } else if (vt == EVT::i32) {
int32_t i_val = (int32_t) CN->getZExtValue();
short s_val = (short) i_val;
return i_val == s_val;
@@ -132,8 +132,8 @@ namespace {
static bool
isFPS16Immediate(ConstantFPSDNode *FPN, short &Imm)
{
- MVT vt = FPN->getValueType(0);
- if (vt == MVT::f32) {
+ EVT vt = FPN->getValueType(0);
+ if (vt == EVT::f32) {
int val = FloatToBits(FPN->getValueAPF().convertToFloat());
int sval = (int) ((val << 16) >> 16);
Imm = (short) val;
@@ -154,34 +154,34 @@ namespace {
}
//===------------------------------------------------------------------===//
- //! MVT to "useful stuff" mapping structure:
+ //! EVT to "useful stuff" mapping structure:
struct valtype_map_s {
- MVT VT;
+ EVT VT;
unsigned ldresult_ins; /// LDRESULT instruction (0 = undefined)
bool ldresult_imm; /// LDRESULT instruction requires immediate?
unsigned lrinst; /// LR instruction
};
const valtype_map_s valtype_map[] = {
- { MVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
- { MVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
- { MVT::i32, SPU::ORIr32, true, SPU::LRr32 },
- { MVT::i64, SPU::ORr64, false, SPU::LRr64 },
- { MVT::f32, SPU::ORf32, false, SPU::LRf32 },
- { MVT::f64, SPU::ORf64, false, SPU::LRf64 },
+ { EVT::i8, SPU::ORBIr8, true, SPU::LRr8 },
+ { EVT::i16, SPU::ORHIr16, true, SPU::LRr16 },
+ { EVT::i32, SPU::ORIr32, true, SPU::LRr32 },
+ { EVT::i64, SPU::ORr64, false, SPU::LRr64 },
+ { EVT::f32, SPU::ORf32, false, SPU::LRf32 },
+ { EVT::f64, SPU::ORf64, false, SPU::LRf64 },
// vector types... (sigh!)
- { MVT::v16i8, 0, false, SPU::LRv16i8 },
- { MVT::v8i16, 0, false, SPU::LRv8i16 },
- { MVT::v4i32, 0, false, SPU::LRv4i32 },
- { MVT::v2i64, 0, false, SPU::LRv2i64 },
- { MVT::v4f32, 0, false, SPU::LRv4f32 },
- { MVT::v2f64, 0, false, SPU::LRv2f64 }
+ { EVT::v16i8, 0, false, SPU::LRv16i8 },
+ { EVT::v8i16, 0, false, SPU::LRv8i16 },
+ { EVT::v4i32, 0, false, SPU::LRv4i32 },
+ { EVT::v2i64, 0, false, SPU::LRv2i64 },
+ { EVT::v4f32, 0, false, SPU::LRv4f32 },
+ { EVT::v2f64, 0, false, SPU::LRv2f64 }
};
const size_t n_valtype_map = sizeof(valtype_map) / sizeof(valtype_map[0]);
- const valtype_map_s *getValueTypeMapEntry(MVT VT)
+ const valtype_map_s *getValueTypeMapEntry(EVT VT)
{
const valtype_map_s *retval = 0;
for (size_t i = 0; i < n_valtype_map; ++i) {
@@ -197,7 +197,7 @@ namespace {
std::string msg;
raw_string_ostream Msg(msg);
Msg << "SPUISelDAGToDAG.cpp: getValueTypeMapEntry returns NULL for "
- << VT.getMVTString();
+ << VT.getEVTString();
llvm_report_error(Msg.str());
}
#endif
@@ -211,12 +211,12 @@ namespace {
// Create the shuffle mask for "rotating" the borrow up one register slot
// once the borrow is generated.
- ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x80808080, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x04050607, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x80808080, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x80808080, EVT::i32));
- return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
&ShufBytes[0], ShufBytes.size());
}
@@ -226,12 +226,12 @@ namespace {
// Create the shuffle mask for "rotating" the borrow up one register slot
// once the borrow is generated.
- ShufBytes.push_back(DAG.getConstant(0x04050607, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, MVT::i32));
- ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, MVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x04050607, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0x0c0d0e0f, EVT::i32));
+ ShufBytes.push_back(DAG.getConstant(0xc0c0c0c0, EVT::i32));
- return DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
&ShufBytes[0], ShufBytes.size());
}
@@ -263,13 +263,13 @@ namespace {
/// getI32Imm - Return a target constant with the specified value, of type
/// i32.
inline SDValue getI32Imm(uint32_t Imm) {
- return CurDAG->getTargetConstant(Imm, MVT::i32);
+ return CurDAG->getTargetConstant(Imm, EVT::i32);
}
/// getI64Imm - Return a target constant with the specified value, of type
/// i64.
inline SDValue getI64Imm(uint64_t Imm) {
- return CurDAG->getTargetConstant(Imm, MVT::i64);
+ return CurDAG->getTargetConstant(Imm, EVT::i64);
}
/// getSmallIPtrImm - Return a target constant of pointer type.
@@ -278,24 +278,24 @@ namespace {
}
SDNode *emitBuildVector(SDValue build_vec) {
- MVT vecVT = build_vec.getValueType();
- MVT eltVT = vecVT.getVectorElementType();
+ EVT vecVT = build_vec.getValueType();
+ EVT eltVT = vecVT.getVectorElementType();
SDNode *bvNode = build_vec.getNode();
DebugLoc dl = bvNode->getDebugLoc();
// Check to see if this vector can be represented as a CellSPU immediate
// constant by invoking all of the instruction selection predicates:
- if (((vecVT == MVT::v8i16) &&
- (SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i16).getNode() != 0)) ||
- ((vecVT == MVT::v4i32) &&
- ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
- (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
- (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i32).getNode() != 0) ||
+ if (((vecVT == EVT::v8i16) &&
+ (SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i16).getNode() != 0)) ||
+ ((vecVT == EVT::v4i32) &&
+ ((SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
+ (SPU::get_ILHUvec_imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
+ (SPU::get_vec_u18imm(bvNode, *CurDAG, EVT::i32).getNode() != 0) ||
(SPU::get_v4i32_imm(bvNode, *CurDAG).getNode() != 0))) ||
- ((vecVT == MVT::v2i64) &&
- ((SPU::get_vec_i16imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
- (SPU::get_ILHUvec_imm(bvNode, *CurDAG, MVT::i64).getNode() != 0) ||
- (SPU::get_vec_u18imm(bvNode, *CurDAG, MVT::i64).getNode() != 0))))
+ ((vecVT == EVT::v2i64) &&
+ ((SPU::get_vec_i16imm(bvNode, *CurDAG, EVT::i64).getNode() != 0) ||
+ (SPU::get_ILHUvec_imm(bvNode, *CurDAG, EVT::i64).getNode() != 0) ||
+ (SPU::get_vec_u18imm(bvNode, *CurDAG, EVT::i64).getNode() != 0))))
return Select(build_vec);
// No, need to emit a constant pool spill:
@@ -323,19 +323,19 @@ namespace {
SDNode *Select(SDValue Op);
//! Emit the instruction sequence for i64 shl
- SDNode *SelectSHLi64(SDValue &Op, MVT OpVT);
+ SDNode *SelectSHLi64(SDValue &Op, EVT OpVT);
//! Emit the instruction sequence for i64 srl
- SDNode *SelectSRLi64(SDValue &Op, MVT OpVT);
+ SDNode *SelectSRLi64(SDValue &Op, EVT OpVT);
//! Emit the instruction sequence for i64 sra
- SDNode *SelectSRAi64(SDValue &Op, MVT OpVT);
+ SDNode *SelectSRAi64(SDValue &Op, EVT OpVT);
//! Emit the necessary sequence for loading i64 constants:
- SDNode *SelectI64Constant(SDValue &Op, MVT OpVT, DebugLoc dl);
+ SDNode *SelectI64Constant(SDValue &Op, EVT OpVT, DebugLoc dl);
//! Alternate instruction emit sequence for loading i64 constants
- SDNode *SelectI64Constant(uint64_t i64const, MVT OpVT, DebugLoc dl);
+ SDNode *SelectI64Constant(uint64_t i64const, EVT OpVT, DebugLoc dl);
//! Returns true if the address N is an A-form (local store) address
bool SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
@@ -434,7 +434,7 @@ bool
SPUDAGToDAGISel::SelectAFormAddr(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index) {
// These match the addr256k operand type:
- MVT OffsVT = MVT::i16;
+ EVT OffsVT = EVT::i16;
SDValue Zero = CurDAG->getTargetConstant(0, OffsVT);
switch (N.getOpcode()) {
@@ -514,7 +514,7 @@ SPUDAGToDAGISel::DFormAddressPredicate(SDValue Op, SDValue N, SDValue &Base,
SDValue &Index, int minOffset,
int maxOffset) {
unsigned Opc = N.getOpcode();
- MVT PtrTy = SPUtli.getPointerTy();
+ EVT PtrTy = SPUtli.getPointerTy();
if (Opc == ISD::FrameIndex) {
// Stack frame index must be less than 512 (divided by 16):
@@ -692,7 +692,7 @@ SPUDAGToDAGISel::Select(SDValue Op) {
unsigned Opc = N->getOpcode();
int n_ops = -1;
unsigned NewOpc;
- MVT OpVT = Op.getValueType();
+ EVT OpVT = Op.getValueType();
SDValue Ops[8];
DebugLoc dl = N->getDebugLoc();
@@ -717,45 +717,45 @@ SPUDAGToDAGISel::Select(SDValue Op) {
TFI, Imm0), 0);
n_ops = 2;
}
- } else if (Opc == ISD::Constant && OpVT == MVT::i64) {
+ } else if (Opc == ISD::Constant && OpVT == EVT::i64) {
// Catch the i64 constants that end up here. Note: The backend doesn't
// attempt to legalize the constant (it's useless because DAGCombiner
// will insert 64-bit constants and we can't stop it).
return SelectI64Constant(Op, OpVT, Op.getDebugLoc());
} else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND)
- && OpVT == MVT::i64) {
+ && OpVT == EVT::i64) {
SDValue Op0 = Op.getOperand(0);
- MVT Op0VT = Op0.getValueType();
- MVT Op0VecVT = MVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
- MVT OpVecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT Op0VT = Op0.getValueType();
+ EVT Op0VecVT = EVT::getVectorVT(Op0VT, (128 / Op0VT.getSizeInBits()));
+ EVT OpVecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
SDValue shufMask;
switch (Op0VT.getSimpleVT()) {
default:
- llvm_report_error("CellSPU Select: Unhandled zero/any extend MVT");
+ llvm_report_error("CellSPU Select: Unhandled zero/any extend EVT");
/*NOTREACHED*/
- case MVT::i32:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x00010203, MVT::i32),
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x08090a0b, MVT::i32));
+ case EVT::i32:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x00010203, EVT::i32),
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x08090a0b, EVT::i32));
break;
- case MVT::i16:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x80800203, MVT::i32),
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x80800a0b, MVT::i32));
+ case EVT::i16:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x80800203, EVT::i32),
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x80800a0b, EVT::i32));
break;
- case MVT::i8:
- shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x80808003, MVT::i32),
- CurDAG->getConstant(0x80808080, MVT::i32),
- CurDAG->getConstant(0x8080800b, MVT::i32));
+ case EVT::i8:
+ shufMask = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v4i32,
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x80808003, EVT::i32),
+ CurDAG->getConstant(0x80808080, EVT::i32),
+ CurDAG->getConstant(0x8080800b, EVT::i32));
break;
}
@@ -775,21 +775,21 @@ SPUDAGToDAGISel::Select(SDValue Op) {
SelectCode(CurDAG->getNode(ISD::BIT_CONVERT, dl, OpVecVT, zextShuffle));
return SelectCode(CurDAG->getNode(SPUISD::VEC2PREFSLOT, dl, OpVT,
zextShuffle));
- } else if (Opc == ISD::ADD && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+ } else if (Opc == ISD::ADD && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
return SelectCode(CurDAG->getNode(SPUISD::ADD64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
- } else if (Opc == ISD::SUB && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+ } else if (Opc == ISD::SUB && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getBorrowGenerateShufMask(*CurDAG, dl));
return SelectCode(CurDAG->getNode(SPUISD::SUB64_MARKER, dl, OpVT,
Op.getOperand(0), Op.getOperand(1),
SDValue(CGLoad, 0)));
- } else if (Opc == ISD::MUL && (OpVT == MVT::i64 || OpVT == MVT::v2i64)) {
+ } else if (Opc == ISD::MUL && (OpVT == EVT::i64 || OpVT == EVT::v2i64)) {
SDNode *CGLoad =
emitBuildVector(getCarryGenerateShufMask(*CurDAG, dl));
@@ -799,8 +799,8 @@ SPUDAGToDAGISel::Select(SDValue Op) {
} else if (Opc == ISD::TRUNCATE) {
SDValue Op0 = Op.getOperand(0);
if ((Op0.getOpcode() == ISD::SRA || Op0.getOpcode() == ISD::SRL)
- && OpVT == MVT::i32
- && Op0.getValueType() == MVT::i64) {
+ && OpVT == EVT::i32
+ && Op0.getValueType() == EVT::i64) {
// Catch (truncate:i32 ([sra|srl]:i64 arg, c), where c >= 32
//
// Take advantage of the fact that the upper 32 bits are in the
@@ -817,7 +817,7 @@ SPUDAGToDAGISel::Select(SDValue Op) {
shift_amt -= 32;
if (shift_amt > 0) {
// Take care of the additional shift, if present:
- SDValue shift = CurDAG->getTargetConstant(shift_amt, MVT::i32);
+ SDValue shift = CurDAG->getTargetConstant(shift_amt, EVT::i32);
unsigned Opc = SPU::ROTMAIr32_i32;
if (Op0.getOpcode() == ISD::SRL)
@@ -832,19 +832,19 @@ SPUDAGToDAGISel::Select(SDValue Op) {
}
}
} else if (Opc == ISD::SHL) {
- if (OpVT == MVT::i64) {
+ if (OpVT == EVT::i64) {
return SelectSHLi64(Op, OpVT);
}
} else if (Opc == ISD::SRL) {
- if (OpVT == MVT::i64) {
+ if (OpVT == EVT::i64) {
return SelectSRLi64(Op, OpVT);
}
} else if (Opc == ISD::SRA) {
- if (OpVT == MVT::i64) {
+ if (OpVT == EVT::i64) {
return SelectSRAi64(Op, OpVT);
}
} else if (Opc == ISD::FNEG
- && (OpVT == MVT::f64 || OpVT == MVT::v2f64)) {
+ && (OpVT == EVT::f64 || OpVT == EVT::v2f64)) {
DebugLoc dl = Op.getDebugLoc();
// Check if the pattern is a special form of DFNMS:
// (fneg (fsub (fmul R64FP:$rA, R64FP:$rB), R64FP:$rC))
@@ -853,7 +853,7 @@ SPUDAGToDAGISel::Select(SDValue Op) {
SDValue Op00 = Op0.getOperand(0);
if (Op00.getOpcode() == ISD::FMUL) {
unsigned Opc = SPU::DFNMSf64;
- if (OpVT == MVT::v2f64)
+ if (OpVT == EVT::v2f64)
Opc = SPU::DFNMSv2f64;
return CurDAG->getTargetNode(Opc, dl, OpVT,
@@ -863,29 +863,29 @@ SPUDAGToDAGISel::Select(SDValue Op) {
}
}
- SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, MVT::i64);
+ SDValue negConst = CurDAG->getConstant(0x8000000000000000ULL, EVT::i64);
SDNode *signMask = 0;
unsigned Opc = SPU::XORfneg64;
- if (OpVT == MVT::f64) {
- signMask = SelectI64Constant(negConst, MVT::i64, dl);
- } else if (OpVT == MVT::v2f64) {
+ if (OpVT == EVT::f64) {
+ signMask = SelectI64Constant(negConst, EVT::i64, dl);
+ } else if (OpVT == EVT::v2f64) {
Opc = SPU::XORfnegvec;
signMask = emitBuildVector(CurDAG->getNode(ISD::BUILD_VECTOR, dl,
- MVT::v2i64,
+ EVT::v2i64,
negConst, negConst));
}
return CurDAG->getTargetNode(Opc, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
} else if (Opc == ISD::FABS) {
- if (OpVT == MVT::f64) {
- SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, MVT::i64, dl);
+ if (OpVT == EVT::f64) {
+ SDNode *signMask = SelectI64Constant(0x7fffffffffffffffULL, EVT::i64, dl);
return CurDAG->getTargetNode(SPU::ANDfabs64, dl, OpVT,
Op.getOperand(0), SDValue(signMask, 0));
- } else if (OpVT == MVT::v2f64) {
- SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, MVT::i64);
- SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64,
+ } else if (OpVT == EVT::v2f64) {
+ SDValue absConst = CurDAG->getConstant(0x7fffffffffffffffULL, EVT::i64);
+ SDValue absVec = CurDAG->getNode(ISD::BUILD_VECTOR, dl, EVT::v2i64,
absConst, absConst);
SDNode *signMask = emitBuildVector(absVec);
return CurDAG->getTargetNode(SPU::ANDfabsvec, dl, OpVT,
@@ -893,7 +893,7 @@ SPUDAGToDAGISel::Select(SDValue Op) {
}
} else if (Opc == SPUISD::LDRESULT) {
// Custom select instructions for LDRESULT
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
SDValue Arg = N->getOperand(0);
SDValue Chain = N->getOperand(1);
SDNode *Result;
@@ -903,7 +903,7 @@ SPUDAGToDAGISel::Select(SDValue Op) {
std::string msg;
raw_string_ostream Msg(msg);
Msg << "LDRESULT for unsupported type: "
- << VT.getMVTString();
+ << VT.getEVTString();
llvm_report_error(Msg.str());
}
@@ -911,9 +911,9 @@ SPUDAGToDAGISel::Select(SDValue Op) {
if (vtm->ldresult_imm) {
SDValue Zero = CurDAG->getTargetConstant(0, VT);
- Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Zero, Chain);
+ Result = CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Arg, Zero, Chain);
} else {
- Result = CurDAG->getTargetNode(Opc, dl, VT, MVT::Other, Arg, Arg, Chain);
+ Result = CurDAG->getTargetNode(Opc, dl, VT, EVT::Other, Arg, Arg, Chain);
}
return Result;
@@ -924,7 +924,7 @@ SPUDAGToDAGISel::Select(SDValue Op) {
// SPUInstrInfo catches the following patterns:
// (SPUindirect (SPUhi ...), (SPUlo ...))
// (SPUindirect $sp, imm)
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue Op0 = N->getOperand(0);
SDValue Op1 = N->getOperand(1);
RegisterSDNode *RN;
@@ -967,17 +967,17 @@ SPUDAGToDAGISel::Select(SDValue Op) {
* @return The SDNode with the entire instruction sequence
*/
SDNode *
-SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) {
+SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, EVT OpVT) {
SDValue Op0 = Op.getOperand(0);
- MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
- MVT ShiftAmtVT = ShiftAmt.getValueType();
+ EVT ShiftAmtVT = ShiftAmt.getValueType();
SDNode *VecOp0, *SelMask, *ZeroFill, *Shift = 0;
SDValue SelMaskVal;
DebugLoc dl = Op.getDebugLoc();
VecOp0 = CurDAG->getTargetNode(SPU::ORv2i64_i64, dl, VecVT, Op0);
- SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, MVT::i16);
+ SelMaskVal = CurDAG->getTargetConstant(0xff00ULL, EVT::i16);
SelMask = CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT, SelMaskVal);
ZeroFill = CurDAG->getTargetNode(SPU::ILv2i64, dl, VecVT,
CurDAG->getTargetConstant(0, OpVT));
@@ -1032,11 +1032,11 @@ SPUDAGToDAGISel::SelectSHLi64(SDValue &Op, MVT OpVT) {
* @return The SDNode with the entire instruction sequence
*/
SDNode *
-SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) {
+SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, EVT OpVT) {
SDValue Op0 = Op.getOperand(0);
- MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
- MVT ShiftAmtVT = ShiftAmt.getValueType();
+ EVT ShiftAmtVT = ShiftAmt.getValueType();
SDNode *VecOp0, *Shift = 0;
DebugLoc dl = Op.getDebugLoc();
@@ -1098,11 +1098,11 @@ SPUDAGToDAGISel::SelectSRLi64(SDValue &Op, MVT OpVT) {
* @return The SDNode with the entire instruction sequence
*/
SDNode *
-SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) {
+SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, EVT OpVT) {
// Promote Op0 to vector
- MVT VecVT = MVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
+ EVT VecVT = EVT::getVectorVT(OpVT, (128 / OpVT.getSizeInBits()));
SDValue ShiftAmt = Op.getOperand(1);
- MVT ShiftAmtVT = ShiftAmt.getValueType();
+ EVT ShiftAmtVT = ShiftAmt.getValueType();
DebugLoc dl = Op.getDebugLoc();
SDNode *VecOp0 =
@@ -1110,16 +1110,16 @@ SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) {
SDValue SignRotAmt = CurDAG->getTargetConstant(31, ShiftAmtVT);
SDNode *SignRot =
- CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, MVT::v2i64,
+ CurDAG->getTargetNode(SPU::ROTMAIv2i64_i32, dl, EVT::v2i64,
SDValue(VecOp0, 0), SignRotAmt);
SDNode *UpperHalfSign =
- CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, MVT::i32, SDValue(SignRot, 0));
+ CurDAG->getTargetNode(SPU::ORi32_v4i32, dl, EVT::i32, SDValue(SignRot, 0));
SDNode *UpperHalfSignMask =
CurDAG->getTargetNode(SPU::FSM64r32, dl, VecVT, SDValue(UpperHalfSign, 0));
SDNode *UpperLowerMask =
CurDAG->getTargetNode(SPU::FSMBIv2i64, dl, VecVT,
- CurDAG->getTargetConstant(0xff00ULL, MVT::i16));
+ CurDAG->getTargetConstant(0xff00ULL, EVT::i16));
SDNode *UpperLowerSelect =
CurDAG->getTargetNode(SPU::SELBv2i64, dl, VecVT,
SDValue(UpperHalfSignMask, 0),
@@ -1166,15 +1166,15 @@ SPUDAGToDAGISel::SelectSRAi64(SDValue &Op, MVT OpVT) {
/*!
Do the necessary magic necessary to load a i64 constant
*/
-SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, MVT OpVT,
+SDNode *SPUDAGToDAGISel::SelectI64Constant(SDValue& Op, EVT OpVT,
DebugLoc dl) {
ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
return SelectI64Constant(CN->getZExtValue(), OpVT, dl);
}
-SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, MVT OpVT,
+SDNode *SPUDAGToDAGISel::SelectI64Constant(uint64_t Value64, EVT OpVT,
DebugLoc dl) {
- MVT OpVecVT = MVT::getVectorVT(OpVT, 2);
+ EVT OpVecVT = EVT::getVectorVT(OpVT, 2);
SDValue i64vec =
SPU::LowerV2I64Splat(OpVecVT, *CurDAG, Value64, dl);
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