diff options
Diffstat (limited to 'llvm/lib/Target/Alpha')
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp | 6 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaISelLowering.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaInstrInfo.cpp | 10 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaJITInfo.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp | 8 | ||||
| -rw-r--r-- | llvm/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp | 8 |
7 files changed, 28 insertions, 28 deletions
diff --git a/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp b/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp index 9a7c5a4f86b..98eeb8983e6 100644 --- a/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp +++ b/llvm/lib/Target/Alpha/AlphaCodeEmitter.cpp @@ -166,7 +166,7 @@ static unsigned getAlphaRegNumber(unsigned Reg) { case Alpha::R30 : case Alpha::F30 : return 30; case Alpha::R31 : case Alpha::F31 : return 31; default: - LLVM_UNREACHABLE("Unhandled reg"); + llvm_unreachable("Unhandled reg"); } } @@ -217,7 +217,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, Offset = MI.getOperand(3).getImm(); break; default: - LLVM_UNREACHABLE("unknown relocatable instruction"); + llvm_unreachable("unknown relocatable instruction"); } if (MO.isGlobal()) MCE.addRelocation(MachineRelocation::getGV(MCE.getCurrentPCOffset(), @@ -238,7 +238,7 @@ unsigned AlphaCodeEmitter::getMachineOpValue(const MachineInstr &MI, #ifndef NDEBUG cerr << "ERROR: Unknown type of MachineOperand: " << MO << "\n"; #endif - llvm_unreachable(); + llvm_unreachable(0); } return rv; diff --git a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp index 977e621b650..0f4d0f42ca2 100644 --- a/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelDAGToDAG.cpp @@ -338,7 +338,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) { bool rev = false; bool inv = false; switch(CC) { - default: DEBUG(N->dump(CurDAG)); LLVM_UNREACHABLE("Unknown FP comparison!"); + default: DEBUG(N->dump(CurDAG)); llvm_unreachable("Unknown FP comparison!"); case ISD::SETEQ: case ISD::SETOEQ: case ISD::SETUEQ: Opc = Alpha::CMPTEQ; break; case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: @@ -472,7 +472,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { } else if (TypeOperands[i] == MVT::f64) { Opc = Alpha::STT; } else - LLVM_UNREACHABLE("Unknown operand"); + llvm_unreachable("Unknown operand"); SDValue Ops[] = { CallOperands[i], getI64Imm((i - 6) * 8), CurDAG->getCopyFromReg(Chain, dl, Alpha::R30, MVT::i64), @@ -489,7 +489,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { CallOperands[i], InFlag); InFlag = Chain.getValue(1); } else - LLVM_UNREACHABLE("Unknown operand"); + llvm_unreachable("Unknown operand"); } // Finally, once everything is in registers to pass to the call, emit the @@ -512,7 +512,7 @@ void AlphaDAGToDAGISel::SelectCALL(SDValue Op) { std::vector<SDValue> CallResults; switch (N->getValueType(0).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ret value!"); + default: llvm_unreachable("Unexpected ret value!"); case MVT::Other: break; case MVT::i64: Chain = CurDAG->getCopyFromReg(Chain, dl, diff --git a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp index 289353631e8..9097a8a9de7 100644 --- a/llvm/lib/Target/Alpha/AlphaISelLowering.cpp +++ b/llvm/lib/Target/Alpha/AlphaISelLowering.cpp @@ -314,7 +314,7 @@ static SDValue LowerRET(SDValue Op, SelectionDAG &DAG) { SDValue()); switch (Op.getNumOperands()) { default: - LLVM_UNREACHABLE("Do not know how to return this many arguments!"); + llvm_unreachable("Do not know how to return this many arguments!"); case 1: break; //return SDValue(); // ret void is legal @@ -380,7 +380,7 @@ AlphaTargetLowering::LowerCallTo(SDValue Chain, const Type *RetTy, for (unsigned i = 0, e = Args.size(); i != e; ++i) { switch (getValueType(Args[i].Ty).getSimpleVT()) { - default: LLVM_UNREACHABLE("Unexpected ValueType for argument!"); + default: llvm_unreachable("Unexpected ValueType for argument!"); case MVT::i1: case MVT::i8: case MVT::i16: @@ -476,7 +476,7 @@ void AlphaTargetLowering::LowerVAARG(SDNode *N, SDValue &Chain, SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { DebugLoc dl = Op.getDebugLoc(); switch (Op.getOpcode()) { - default: LLVM_UNREACHABLE("Wasn't expecting to be able to lower this!"); + default: llvm_unreachable("Wasn't expecting to be able to lower this!"); case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG, VarArgsBase, VarArgsOffset); @@ -527,7 +527,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { return Lo; } case ISD::GlobalTLSAddress: - LLVM_UNREACHABLE("TLS not implemented for Alpha."); + llvm_unreachable("TLS not implemented for Alpha."); case ISD::GlobalAddress: { GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op); GlobalValue *GV = GSDN->getGlobal(); diff --git a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp index 139a4db655c..3cb2ce3720d 100644 --- a/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaInstrInfo.cpp @@ -201,7 +201,7 @@ AlphaInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, .addReg(SrcReg, getKillRegState(isKill)) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); } void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, @@ -217,7 +217,7 @@ void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::STQ; else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)); @@ -246,7 +246,7 @@ AlphaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg) .addFrameIndex(FrameIdx).addReg(Alpha::F31); else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); } void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, @@ -261,7 +261,7 @@ void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, else if (RC == Alpha::GPRCRegisterClass) Opc = Alpha::LDQ; else - LLVM_UNREACHABLE("Unhandled register class"); + llvm_unreachable("Unhandled register class"); DebugLoc DL = DebugLoc::getUnknownLoc(); MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg); @@ -332,7 +332,7 @@ static unsigned AlphaRevCondCode(unsigned Opcode) { case Alpha::FBLE: return Alpha::FBGT; case Alpha::FBLT: return Alpha::FBGE; default: - LLVM_UNREACHABLE("Unknown opcode"); + llvm_unreachable("Unknown opcode"); } return 0; // Not reached } diff --git a/llvm/lib/Target/Alpha/AlphaJITInfo.cpp b/llvm/lib/Target/Alpha/AlphaJITInfo.cpp index 8919dc0492b..4feb2776ec6 100644 --- a/llvm/lib/Target/Alpha/AlphaJITInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaJITInfo.cpp @@ -72,7 +72,7 @@ static void EmitBranchToAt(void *At, void *To) { void AlphaJITInfo::replaceMachineCodeForFunction(void *Old, void *New) { //FIXME - llvm_unreachable(); + llvm_unreachable(0); } static TargetJITInfo::JITCompilerFn JITCompilerFunction; @@ -185,7 +185,7 @@ extern "C" { ); #else void AlphaCompilationCallback() { - LLVM_UNREACHABLE("Cannot call AlphaCompilationCallback() on a non-Alpha arch!"); + llvm_unreachable("Cannot call AlphaCompilationCallback() on a non-Alpha arch!"); } #endif } @@ -241,7 +241,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR, long idx = 0; bool doCommon = true; switch ((Alpha::RelocationType)MR->getRelocationType()) { - default: LLVM_UNREACHABLE("Unknown relocation type!"); + default: llvm_unreachable("Unknown relocation type!"); case Alpha::reloc_literal: //This is a LDQl idx = MR->getGOTIndex(); @@ -281,7 +281,7 @@ void AlphaJITInfo::relocate(void *Function, MachineRelocation *MR, DOUT << "LDA: " << idx << "\n"; break; default: - LLVM_UNREACHABLE("Cannot handle gpdist yet"); + llvm_unreachable("Cannot handle gpdist yet"); } break; case Alpha::reloc_bsr: { diff --git a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp index f1e651c6a80..0c4a36a61b7 100644 --- a/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp +++ b/llvm/lib/Target/Alpha/AlphaRegisterInfo.cpp @@ -307,7 +307,7 @@ void AlphaRegisterInfo::emitEpilogue(MachineFunction &MF, } unsigned AlphaRegisterInfo::getRARegister() const { - LLVM_UNREACHABLE("What is the return address register"); + llvm_unreachable("What is the return address register"); return 0; } @@ -316,17 +316,17 @@ unsigned AlphaRegisterInfo::getFrameRegister(MachineFunction &MF) const { } unsigned AlphaRegisterInfo::getEHExceptionRegister() const { - LLVM_UNREACHABLE("What is the exception register"); + llvm_unreachable("What is the exception register"); return 0; } unsigned AlphaRegisterInfo::getEHHandlerRegister() const { - LLVM_UNREACHABLE("What is the exception handler register"); + llvm_unreachable("What is the exception handler register"); return 0; } int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const { - LLVM_UNREACHABLE("What is the dwarf register number"); + llvm_unreachable("What is the dwarf register number"); return -1; } diff --git a/llvm/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp b/llvm/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp index 38bdeb25c06..1e3e83c8410 100644 --- a/llvm/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp +++ b/llvm/lib/Target/Alpha/AsmPrinter/AlphaAsmPrinter.cpp @@ -101,7 +101,7 @@ void AlphaAsmPrinter::printOp(const MachineOperand &MO, bool IsCallOp) { return; case MachineOperand::MO_Immediate: - LLVM_UNREACHABLE("printOp() does not handle immediate values"); + llvm_unreachable("printOp() does not handle immediate values"); return; case MachineOperand::MO_MachineBasicBlock: @@ -155,7 +155,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) { EmitAlignment(MF.getAlignment(), F); switch (F->getLinkage()) { - default: LLVM_UNREACHABLE("Unknown linkage type!"); + default: llvm_unreachable("Unknown linkage type!"); case Function::InternalLinkage: // Symbols default to internal. case Function::PrivateLinkage: break; @@ -188,7 +188,7 @@ bool AlphaAsmPrinter::runOnMachineFunction(MachineFunction &MF) { // Print the assembly for the instruction. ++EmittedInsts; if (!printInstruction(II)) { - LLVM_UNREACHABLE("Unhandled instruction in asm writer!"); + llvm_unreachable("Unhandled instruction in asm writer!"); } } } @@ -248,7 +248,7 @@ void AlphaAsmPrinter::printModuleLevelGV(const GlobalVariable* GVar) { case GlobalValue::PrivateLinkage: break; default: - LLVM_UNREACHABLE("Unknown linkage type!"); + llvm_unreachable("Unknown linkage type!"); } // 3: Type, Size, Align |
