diff options
Diffstat (limited to 'llvm/lib/Target/ARM64')
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64.td | 14 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64InstrFormats.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64InstrInfo.td | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64Subtarget.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64Subtarget.h | 2 |
5 files changed, 18 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64.td b/llvm/lib/Target/ARM64/ARM64.td index 69a126ce6a8..653f1574158 100644 --- a/llvm/lib/Target/ARM64/ARM64.td +++ b/llvm/lib/Target/ARM64/ARM64.td @@ -29,6 +29,9 @@ def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true", def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true", "Enable cryptographic instructions">; +def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true", + "Enable ARMv8 CRC-32 checksum instructions">; + /// Cyclone has register move instructions which are "free". def FeatureZCRegMove : SubtargetFeature<"zcm", "HasZeroCycleRegMove", "true", "Has zereo-cycle register moves">; @@ -63,22 +66,27 @@ def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53", "Cortex-A53 ARM processors", [FeatureFPARMv8, FeatureNEON, - FeatureCrypto]>; + FeatureCrypto, + FeatureCRC]>; def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57", "Cortex-A57 ARM processors", [FeatureFPARMv8, FeatureNEON, - FeatureCrypto]>; + FeatureCrypto, + FeatureCRC]>; def ProcCyclone : SubtargetFeature<"cyclone", "ARMProcFamily", "Cyclone", "Cyclone", [FeatureFPARMv8, FeatureNEON, FeatureCrypto, + FeatureCRC, FeatureZCRegMove, FeatureZCZeroing]>; -def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8, FeatureNEON]>; +def : ProcessorModel<"generic", NoSchedModel, [FeatureFPARMv8, + FeatureNEON, + FeatureCRC]>; def : ProcessorModel<"cortex-a53", CortexA53Model, [ProcA53]>; def : ProcessorModel<"cortex-a57", NoSchedModel, [ProcA57]>; diff --git a/llvm/lib/Target/ARM64/ARM64InstrFormats.td b/llvm/lib/Target/ARM64/ARM64InstrFormats.td index 94fc2e0ab9f..2db7449d6aa 100644 --- a/llvm/lib/Target/ARM64/ARM64InstrFormats.td +++ b/llvm/lib/Target/ARM64/ARM64InstrFormats.td @@ -1243,6 +1243,7 @@ class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg, let Inst{11-10} = sz; let Inst{9-5} = Rn; let Inst{4-0} = Rd; + let Predicates = [HasCRC]; } //--- diff --git a/llvm/lib/Target/ARM64/ARM64InstrInfo.td b/llvm/lib/Target/ARM64/ARM64InstrInfo.td index e4b47d7355d..ddcedee04c3 100644 --- a/llvm/lib/Target/ARM64/ARM64InstrInfo.td +++ b/llvm/lib/Target/ARM64/ARM64InstrInfo.td @@ -18,8 +18,10 @@ def HasFPARMv8 : Predicate<"Subtarget->hasFPARMv8()">, AssemblerPredicate<"FeatureFPARMv8", "fp-armv8">; def HasNEON : Predicate<"Subtarget->hasNEON()">, AssemblerPredicate<"FeatureNEON", "neon">; -def HasCrypto : Predicate<"Subtarget->hasCrypto()">, +def HasCrypto : Predicate<"Subtarget->hasCrypto()">, AssemblerPredicate<"FeatureCrypto", "crypto">; +def HasCRC : Predicate<"Subtarget->hasCRC()">, + AssemblerPredicate<"FeatureCRC", "crc">; //===----------------------------------------------------------------------===// // ARM64-specific DAG Nodes. diff --git a/llvm/lib/Target/ARM64/ARM64Subtarget.cpp b/llvm/lib/Target/ARM64/ARM64Subtarget.cpp index abe8e054ddf..e7cafbb3047 100644 --- a/llvm/lib/Target/ARM64/ARM64Subtarget.cpp +++ b/llvm/lib/Target/ARM64/ARM64Subtarget.cpp @@ -29,7 +29,7 @@ using namespace llvm; ARM64Subtarget::ARM64Subtarget(const std::string &TT, const std::string &CPU, const std::string &FS, bool LittleEndian) : ARM64GenSubtargetInfo(TT, CPU, FS), ARMProcFamily(Others), - HasFPARMv8(false), HasNEON(false), HasCrypto(false), + HasFPARMv8(false), HasNEON(false), HasCrypto(false), HasCRC(false), HasZeroCycleRegMove(false), HasZeroCycleZeroing(false), CPUString(CPU), TargetTriple(TT), IsLittleEndian(LittleEndian) { // Determine default and user-specified characteristics diff --git a/llvm/lib/Target/ARM64/ARM64Subtarget.h b/llvm/lib/Target/ARM64/ARM64Subtarget.h index 1977e0bf05a..031068c4b86 100644 --- a/llvm/lib/Target/ARM64/ARM64Subtarget.h +++ b/llvm/lib/Target/ARM64/ARM64Subtarget.h @@ -35,6 +35,7 @@ protected: bool HasFPARMv8; bool HasNEON; bool HasCrypto; + bool HasCRC; // HasZeroCycleRegMove - Has zero-cycle register mov instructions. bool HasZeroCycleRegMove; @@ -66,6 +67,7 @@ public: bool hasFPARMv8() const { return HasFPARMv8; } bool hasNEON() const { return HasNEON; } bool hasCrypto() const { return HasCrypto; } + bool hasCRC() const { return HasCRC; } bool isLittleEndian() const { return IsLittleEndian; } |
