summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'llvm/lib/Target/ARM64/ARM64TargetMachine.cpp')
-rw-r--r--llvm/lib/Target/ARM64/ARM64TargetMachine.cpp11
1 files changed, 10 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp b/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp
index 101dc25839e..f4a79963790 100644
--- a/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp
+++ b/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp
@@ -39,6 +39,14 @@ EnableCollectLOH("arm64-collect-loh", cl::Hidden,
" optimization hints (LOH)"),
cl::init(true));
+static cl::opt<bool>
+EnableDeadRegisterElimination("arm64-dead-def-elimination", cl::Hidden,
+ cl::desc("Enable the pass that removes dead"
+ " definitons and replaces stores to"
+ " them with stores to the zero"
+ " register"),
+ cl::init(true));
+
extern "C" void LLVMInitializeARM64Target() {
// Register the target.
RegisterTargetMachine<ARM64TargetMachine> X(TheARM64Target);
@@ -135,7 +143,8 @@ bool ARM64PassConfig::addPreRegAlloc() {
bool ARM64PassConfig::addPostRegAlloc() {
// Change dead register definitions to refer to the zero register.
- addPass(createARM64DeadRegisterDefinitions());
+ if (EnableDeadRegisterElimination)
+ addPass(createARM64DeadRegisterDefinitions());
return true;
}
OpenPOWER on IntegriCloud