diff options
Diffstat (limited to 'llvm/lib/Target/ARM64/ARM64TargetMachine.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64TargetMachine.cpp | 35 |
1 files changed, 30 insertions, 5 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp b/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp index 8070ce0d8b2..7e3228f0230 100644 --- a/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp +++ b/llvm/lib/Target/ARM64/ARM64TargetMachine.cpp @@ -49,7 +49,8 @@ EnableDeadRegisterElimination("arm64-dead-def-elimination", cl::Hidden, extern "C" void LLVMInitializeARM64Target() { // Register the target. - RegisterTargetMachine<ARM64TargetMachine> X(TheARM64Target); + RegisterTargetMachine<ARM64leTargetMachine> X(TheARM64leTarget); + RegisterTargetMachine<ARM64beTargetMachine> Y(TheARM64beTarget); } /// TargetMachine ctor - Create an ARM64 architecture model. @@ -58,16 +59,40 @@ ARM64TargetMachine::ARM64TargetMachine(const Target &T, StringRef TT, StringRef CPU, StringRef FS, const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM, - CodeGenOpt::Level OL) + CodeGenOpt::Level OL, + bool LittleEndian) : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL), - Subtarget(TT, CPU, FS), - DL(Subtarget.isTargetMachO() ? "e-m:o-i64:64-i128:128-n32:64-S128" - : "e-m:e-i64:64-i128:128-n32:64-S128"), + Subtarget(TT, CPU, FS, LittleEndian), + // This nested ternary is horrible, but DL needs to be properly initialized + // before TLInfo is constructed. + DL(Subtarget.isTargetMachO() ? + "e-m:o-i64:64-i128:128-n32:64-S128" : + (LittleEndian ? + "e-m:e-i64:64-i128:128-n32:64-S128" : + "E-m:e-i64:64-i128:128-n32:64-S128")), InstrInfo(Subtarget), TLInfo(*this), FrameLowering(*this, Subtarget), TSInfo(*this) { initAsmInfo(); } +void ARM64leTargetMachine::anchor() { } + +ARM64leTargetMachine:: +ARM64leTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : ARM64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} + +void ARM64beTargetMachine::anchor() { } + +ARM64beTargetMachine:: +ARM64beTargetMachine(const Target &T, StringRef TT, + StringRef CPU, StringRef FS, const TargetOptions &Options, + Reloc::Model RM, CodeModel::Model CM, + CodeGenOpt::Level OL) + : ARM64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} + namespace { /// ARM64 Code Generator Pass Configuration Options. class ARM64PassConfig : public TargetPassConfig { |
