diff options
Diffstat (limited to 'llvm/lib/Target/ARM64/ARM64Schedule.td')
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64Schedule.td | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64Schedule.td b/llvm/lib/Target/ARM64/ARM64Schedule.td index 26a484fa0ad..3a4194173a8 100644 --- a/llvm/lib/Target/ARM64/ARM64Schedule.td +++ b/llvm/lib/Target/ARM64/ARM64Schedule.td @@ -51,7 +51,10 @@ def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled). def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST. // Predicate for determining when a shiftable register is shifted. -def RegShiftedPred : SchedPredicate<[{TII->hasNonZeroImm(MI)}]>; +def RegShiftedPred : SchedPredicate<[{TII->hasShiftedReg(MI)}]>; + +// Predicate for determining when a extendedable register is extended. +def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(MI)}]>; // ScaledIdxPred is true if a WriteLDIdx operand will be // scaled. Subtargets can use this to dynamically select resources and |
