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| author | Chad Rosier <mcrosier@codeaurora.org> | 2014-05-19 22:59:51 +0000 |
|---|---|---|
| committer | Chad Rosier <mcrosier@codeaurora.org> | 2014-05-19 22:59:51 +0000 |
| commit | b06ed63ebf65c9c1d900724ffbacd6dc99e03363 (patch) | |
| tree | 52c16363ed02fe3092fcc132edbe4150ac209bb6 /llvm/lib/Target/ARM64/ARM64Schedule.td | |
| parent | 97b084f52859cc07b1e8c28357dac7f5bbb00dd0 (diff) | |
| download | bcm5719-llvm-b06ed63ebf65c9c1d900724ffbacd6dc99e03363.tar.gz bcm5719-llvm-b06ed63ebf65c9c1d900724ffbacd6dc99e03363.zip | |
[ARM64] Adds Cortex-A53 scheduling support for vector load/store post.
Patch by Dave Estes<cestes@codeaurora.org>!
PR19761 http://reviews.llvm.org/D3829
llvm-svn: 209176
Diffstat (limited to 'llvm/lib/Target/ARM64/ARM64Schedule.td')
| -rw-r--r-- | llvm/lib/Target/ARM64/ARM64Schedule.td | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/llvm/lib/Target/ARM64/ARM64Schedule.td b/llvm/lib/Target/ARM64/ARM64Schedule.td index 26a484fa0ad..3a4194173a8 100644 --- a/llvm/lib/Target/ARM64/ARM64Schedule.td +++ b/llvm/lib/Target/ARM64/ARM64Schedule.td @@ -51,7 +51,10 @@ def WriteSTIdx : SchedWrite; // Store to a register index (maybe scaled). def ReadAdrBase : SchedRead; // Read the base resister of a reg-offset LD/ST. // Predicate for determining when a shiftable register is shifted. -def RegShiftedPred : SchedPredicate<[{TII->hasNonZeroImm(MI)}]>; +def RegShiftedPred : SchedPredicate<[{TII->hasShiftedReg(MI)}]>; + +// Predicate for determining when a extendedable register is extended. +def RegExtendedPred : SchedPredicate<[{TII->hasExtendedReg(MI)}]>; // ScaledIdxPred is true if a WriteLDIdx operand will be // scaled. Subtargets can use this to dynamically select resources and |
