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-rw-r--r--llvm/lib/Target/ARM/ARMTargetMachine.cpp14
1 files changed, 7 insertions, 7 deletions
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 04d2b533c24..a6b56ad7cc6 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -115,11 +115,10 @@ computeTargetABI(const Triple &TT, StringRef CPU,
return TargetABI;
}
-static std::string computeDataLayout(StringRef TT, StringRef CPU,
+static std::string computeDataLayout(const Triple &TT, StringRef CPU,
const TargetOptions &Options,
bool isLittle) {
- const Triple Triple(TT);
- auto ABI = computeTargetABI(Triple, CPU, Options);
+ auto ABI = computeTargetABI(TT, CPU, Options);
std::string Ret = "";
if (isLittle)
@@ -129,7 +128,7 @@ static std::string computeDataLayout(StringRef TT, StringRef CPU,
// Big endian.
Ret += "E";
- Ret += DataLayout::getManglingComponent(Triple);
+ Ret += DataLayout::getManglingComponent(TT);
// Pointers are 32 bits and aligned to 32 bits.
Ret += "-p:32:32";
@@ -159,7 +158,7 @@ static std::string computeDataLayout(StringRef TT, StringRef CPU,
// The stack is 128 bit aligned on NaCl, 64 bit aligned on AAPCS and 32 bit
// aligned everywhere else.
- if (Triple.isOSNaCl())
+ if (TT.isOSNaCl())
Ret += "-S128";
else if (ABI == ARMBaseTargetMachine::ARM_ABI_AAPCS)
Ret += "-S64";
@@ -176,8 +175,9 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, StringRef TT,
const TargetOptions &Options,
Reloc::Model RM, CodeModel::Model CM,
CodeGenOpt::Level OL, bool isLittle)
- : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
- CPU, FS, Options, RM, CM, OL),
+ : LLVMTargetMachine(T,
+ computeDataLayout(Triple(TT), CPU, Options, isLittle),
+ TT, CPU, FS, Options, RM, CM, OL),
TargetABI(computeTargetABI(Triple(TT), CPU, Options)),
TLOF(createTLOF(Triple(getTargetTriple()))),
Subtarget(Triple(TT), CPU, FS, *this, isLittle), isLittle(isLittle) {
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