diff options
Diffstat (limited to 'llvm/lib/Target/ARM/ARMSubtarget.cpp')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMSubtarget.cpp | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index c9316a71bdf..eb4d39b01cb 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -72,6 +72,9 @@ static cl::opt<bool> ForceFastISel("arm-force-fast-isel", cl::init(false), cl::Hidden); +static cl::opt<bool> EnableSubRegLiveness("arm-enable-subreg-liveness", + cl::init(false), cl::Hidden); + /// initializeSubtargetDependencies - Initializes using a CPU and feature string /// so that we can use initializer lists for subtarget initialization. ARMSubtarget &ARMSubtarget::initializeSubtargetDependencies(StringRef CPU, @@ -379,6 +382,8 @@ bool ARMSubtarget::enableMachineScheduler() const { return useMachineScheduler(); } +bool ARMSubtarget::enableSubRegLiveness() const { return EnableSubRegLiveness; } + // This overrides the PostRAScheduler bit in the SchedModel for any CPU. bool ARMSubtarget::enablePostRAScheduler() const { if (enableMachineScheduler()) |
