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-rw-r--r--llvm/lib/Target/ARM/ARMSubtarget.cpp5
1 files changed, 5 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 4c6e69654d5..b91e9ae650c 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -167,6 +167,7 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) {
ArchFS = FS;
}
ParseSubtargetFeatures(CPUString, ArchFS);
+ printf("A-class: %d\n", static_cast<bool>(getFeatureBits()[ARM::ProcSwift]));
// FIXME: This used enable V6T2 support implicitly for Thumb2 mode.
// Assert this for now to make the change obvious.
@@ -285,6 +286,10 @@ bool ARMSubtarget::enableAtomicExpand() const {
return hasAnyDataBarrier() && !isThumb1Only();
}
+bool ARMSubtarget::useStride4VFPs(const MachineFunction &MF) const {
+ return isSwift() && !MF.getFunction()->hasFnAttribute(Attribute::MinSize);
+}
+
bool ARMSubtarget::useMovt(const MachineFunction &MF) const {
// NOTE Windows on ARM needs to use mov.w/mov.t pairs to materialise 32-bit
// immediates as it is inherently position independent, and may be out of
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