1 files changed, 42 insertions, 8 deletions

diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp
index 682eb38e714..29d6d148d91 100644
--- a/llvm/lib/Target/ARM/ARMSubtarget.cpp
+++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp
@@ -28,6 +28,7 @@
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/ADT/Twine.h"
+#include "llvm/CodeGen/GlobalISel/GISelAccessor.h"
 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
@@ -96,6 +97,33 @@ ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU,
   return new ARMFrameLowering(STI);
 }
 
+namespace {
+
+struct ARMGISelActualAccessor : public GISelAccessor {
+  std::unique_ptr<CallLowering> CallLoweringInfo;
+  std::unique_ptr<InstructionSelector> InstSelector;
+  std::unique_ptr<LegalizerInfo> Legalizer;
+  std::unique_ptr<RegisterBankInfo> RegBankInfo;
+
+  const CallLowering *getCallLowering() const override {
+    return CallLoweringInfo.get();
+  }
+
+  const InstructionSelector *getInstructionSelector() const override {
+    return InstSelector.get();
+  }
+
+  const LegalizerInfo *getLegalizerInfo() const override {
+    return Legalizer.get();
+  }
+
+  const RegisterBankInfo *getRegBankInfo() const override {
+    return RegBankInfo.get();
+  }
+};
+
+} // end anonymous namespace
+
 ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
                            const std::string &FS,
                            const ARMBaseTargetMachine &TM, bool IsLittle)
@@ -113,34 +141,40 @@ ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU,
   assert((isThumb() || hasARMOps()) &&
          "Target must either be thumb or support ARM operations!");
 
-  CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
-  Legalizer.reset(new ARMLegalizerInfo(*this));
+  ARMGISelActualAccessor *GISel = new ARMGISelActualAccessor();
+  GISel->CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering()));
+  GISel->Legalizer.reset(new ARMLegalizerInfo(*this));
 
   auto *RBI = new ARMRegisterBankInfo(*getRegisterInfo());
 
   // FIXME: At this point, we can't rely on Subtarget having RBI.
   // It's awkward to mix passing RBI and the Subtarget; should we pass
   // TII/TRI as well?
-  InstSelector.reset(createARMInstructionSelector(
+  GISel->InstSelector.reset(createARMInstructionSelector(
       *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI));
 
-  RegBankInfo.reset(RBI);
+  GISel->RegBankInfo.reset(RBI);
+  setGISelAccessor(*GISel);
 }
 
 const CallLowering *ARMSubtarget::getCallLowering() const {
-  return CallLoweringInfo.get();
+  assert(GISel && "Access to GlobalISel APIs not set");
+  return GISel->getCallLowering();
 }
 
 const InstructionSelector *ARMSubtarget::getInstructionSelector() const {
-  return InstSelector.get();
+  assert(GISel && "Access to GlobalISel APIs not set");
+  return GISel->getInstructionSelector();
 }
 
 const LegalizerInfo *ARMSubtarget::getLegalizerInfo() const {
-  return Legalizer.get();
+  assert(GISel && "Access to GlobalISel APIs not set");
+  return GISel->getLegalizerInfo();
 }
 
 const RegisterBankInfo *ARMSubtarget::getRegBankInfo() const {
-  return RegBankInfo.get();
+  assert(GISel && "Access to GlobalISel APIs not set");
+  return GISel->getRegBankInfo();
 }
 
 bool ARMSubtarget::isXRaySupported() const {