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Diffstat (limited to 'llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp')
-rw-r--r--llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp15
1 files changed, 0 insertions, 15 deletions
diff --git a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 8dca2c35c65..7f34ee96e37 100644
--- a/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/llvm/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -56,8 +56,6 @@ public:
{ "fixup_t2_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
MCFixupKindInfo::FKF_IsAligned},
{ "fixup_arm_adr_pcrel_12", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
-{ "fixup_t2_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel |
- MCFixupKindInfo::FKF_IsAligned},
{ "fixup_arm_branch", 1, 24, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
{ "fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel },
@@ -135,9 +133,6 @@ public:
/// ADR label target.
uint32_t getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
SmallVectorImpl<MCFixup> &Fixups) const;
- uint32_t getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups) const;
-
/// getAddrModeImm12OpValue - Return encoding info for 'reg +/- imm12'
/// operand.
@@ -549,16 +544,6 @@ getAdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
Fixups);
}
-/// getAdrLabelOpValue - Return encoding info for 12-bit immediate ADR label
-/// target.
-uint32_t ARMMCCodeEmitter::
-getT2AdrLabelOpValue(const MCInst &MI, unsigned OpIdx,
- SmallVectorImpl<MCFixup> &Fixups) const {
- assert(MI.getOperand(OpIdx).isExpr() && "Unexpected adr target type!");
- return ::getBranchTargetOpValue(MI, OpIdx, ARM::fixup_t2_adr_pcrel_12,
- Fixups);
-}
-
/// getTAddrModeRegRegOpValue - Return encoding info for 'reg + reg' operand.
uint32_t ARMMCCodeEmitter::
getTAddrModeRegRegOpValue(const MCInst &MI, unsigned OpIdx,
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