diff options
Diffstat (limited to 'llvm/lib/Target/ARM/ARMInstrNEON.td')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMInstrNEON.td | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 3f07d302b03..c7ff523b437 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -201,11 +201,26 @@ class VLD3D<string OpcodeStr> : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3), (ins addrmode6:$addr), IIC_VLD3, !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), "", []>; +class VLD3WB<string OpcodeStr> + : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, GPR:$wb), + (ins addrmode6:$addr), IIC_VLD3, + !strconcat(OpcodeStr, "\t\\{$dst1,$dst2,$dst3\\}, $addr"), + "$addr.addr = $wb", []>; def VLD3d8 : VLD3D<"vld3.8">; def VLD3d16 : VLD3D<"vld3.16">; def VLD3d32 : VLD3D<"vld3.32">; +// vld3 to double-spaced even registers. +def VLD3q8a : VLD3WB<"vld3.8">; +def VLD3q16a : VLD3WB<"vld3.16">; +def VLD3q32a : VLD3WB<"vld3.32">; + +// vld3 to double-spaced odd registers. +def VLD3q8b : VLD3WB<"vld3.8">; +def VLD3q16b : VLD3WB<"vld3.16">; +def VLD3q32b : VLD3WB<"vld3.32">; + // VLD4 : Vector Load (multiple 4-element structures) class VLD4D<string OpcodeStr> : NLdSt<(outs DPR:$dst1, DPR:$dst2, DPR:$dst3, DPR:$dst4), |
