1 files changed, 0 insertions, 47 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.h b/llvm/lib/Target/ARM/ARMInstrInfo.h
index 659ddc0e5ed..90f34ea0840 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.h
@@ -38,53 +38,6 @@ public:
   ///
   const ARMRegisterInfo &getRegisterInfo() const override { return RI; }
 
-  /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
-  /// and \p DefIdx.
-  /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
-  /// the list is modeled as <Reg:SubReg, SubIdx>.
-  /// E.g., REG_SEQUENCE vreg1:sub1, sub0, vreg2, sub1 would produce
-  /// two elements:
-  /// - vreg1:sub1, sub0
-  /// - vreg2<:0>, sub1
-  ///
-  /// \returns true if it is possible to build such an input sequence
-  /// with the pair \p MI, \p DefIdx. False otherwise.
-  ///
-  /// \pre MI.isRegSequenceLike().
-  bool getRegSequenceLikeInputs(
-      const MachineInstr &MI, unsigned DefIdx,
-      SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
-
-  /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
-  /// and \p DefIdx.
-  /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
-  /// E.g., EXTRACT_SUBREG vreg1:sub1, sub0, sub1 would produce:
-  /// - vreg1:sub1, sub0
-  ///
-  /// \returns true if it is possible to build such an input sequence
-  /// with the pair \p MI, \p DefIdx. False otherwise.
-  ///
-  /// \pre MI.isExtractSubregLike().
-  bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
-                                  RegSubRegPairAndIdx &InputReg) const override;
-
-  /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
-  /// and \p DefIdx.
-  /// \p [out] BaseReg and \p [out] InsertedReg contain
-  /// the equivalent inputs of INSERT_SUBREG.
-  /// E.g., INSERT_SUBREG vreg0:sub0, vreg1:sub1, sub3 would produce:
-  /// - BaseReg: vreg0:sub0
-  /// - InsertedReg: vreg1:sub1, sub3
-  ///
-  /// \returns true if it is possible to build such an input sequence
-  /// with the pair \p MI, \p DefIdx. False otherwise.
-  ///
-  /// \pre MI.isInsertSubregLike().
-  bool
-  getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
-                            RegSubRegPair &BaseReg,
-                            RegSubRegPairAndIdx &InsertedReg) const override;
-
 private:
   void expandLoadStackGuard(MachineBasicBlock::iterator MI,
                             Reloc::Model RM) const override;