1 files changed, 0 insertions, 69 deletions
diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.cpp b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
index 5acaa877a3e..512152807e3 100644
--- a/llvm/lib/Target/ARM/ARMInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMInstrInfo.cpp
@@ -98,75 +98,6 @@ void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
     expandLoadStackGuardBase(MI, ARM::LDRLIT_ga_abs, ARM::LDRi12, RM);
 }
 
-bool ARMInstrInfo::getRegSequenceLikeInputs(
-    const MachineInstr &MI, unsigned DefIdx,
-    SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
-  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
-  assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
-
-  switch (MI.getOpcode()) {
-  case ARM::VMOVDRR:
-    // dX = VMOVDRR rY, rZ
-    // is the same as:
-    // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
-    // Populate the InputRegs accordingly.
-    // rY
-    const MachineOperand *MOReg = &MI.getOperand(1);
-    InputRegs.push_back(
-        RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
-    // rZ
-    MOReg = &MI.getOperand(2);
-    InputRegs.push_back(
-        RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
-    return true;
-  }
-  llvm_unreachable("Target dependent opcode missing");
-}
-
-bool ARMInstrInfo::getExtractSubregLikeInputs(
-    const MachineInstr &MI, unsigned DefIdx,
-    RegSubRegPairAndIdx &InputReg) const {
-  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
-  assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
-
-  switch (MI.getOpcode()) {
-  case ARM::VMOVRRD:
-    // rX, rY = VMOVRRD dZ
-    // is the same as:
-    // rX = EXTRACT_SUBREG dZ, ssub_0
-    // rY = EXTRACT_SUBREG dZ, ssub_1
-    const MachineOperand &MOReg = MI.getOperand(2);
-    InputReg.Reg = MOReg.getReg();
-    InputReg.SubReg = MOReg.getSubReg();
-    InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
-    return true;
-  }
-  llvm_unreachable("Target dependent opcode missing");
-}
-
-bool ARMInstrInfo::getInsertSubregLikeInputs(
-    const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
-    RegSubRegPairAndIdx &InsertedReg) const {
-  assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
-  assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
-
-  switch (MI.getOpcode()) {
-  case ARM::VSETLNi32:
-    // dX = VSETLNi32 dY, rZ, imm
-    const MachineOperand &MOBaseReg = MI.getOperand(1);
-    const MachineOperand &MOInsertedReg = MI.getOperand(2);
-    const MachineOperand &MOIndex = MI.getOperand(3);
-    BaseReg.Reg = MOBaseReg.getReg();
-    BaseReg.SubReg = MOBaseReg.getSubReg();
-
-    InsertedReg.Reg = MOInsertedReg.getReg();
-    InsertedReg.SubReg = MOInsertedReg.getSubReg();
-    InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
-    return true;
-  }
-  llvm_unreachable("Target dependent opcode missing");
-}
-
 namespace {
   /// ARMCGBR - Create Global Base Reg pass. This initializes the PIC
   /// global base register for ARM ELF.