diff options
Diffstat (limited to 'llvm/lib/Target/ARM/ARMBaseInfo.h')
| -rw-r--r-- | llvm/lib/Target/ARM/ARMBaseInfo.h | 64 |
1 files changed, 54 insertions, 10 deletions
diff --git a/llvm/lib/Target/ARM/ARMBaseInfo.h b/llvm/lib/Target/ARM/ARMBaseInfo.h index c68471f79e7..70b5b0a2d93 100644 --- a/llvm/lib/Target/ARM/ARMBaseInfo.h +++ b/llvm/lib/Target/ARM/ARMBaseInfo.h @@ -19,6 +19,18 @@ #include "llvm/Support/ErrorHandling.h" +// Note that the following auto-generated files only defined enum types, and +// so are safe to include here. + +// Defines symbolic names for ARM registers. This defines a mapping from +// register name to register number. +// +#include "ARMGenRegisterNames.inc" + +// Defines symbolic names for the ARM instructions. +// +#include "ARMGenInstrNames.inc" + namespace llvm { // Enums corresponding to ARM condition codes @@ -111,18 +123,50 @@ namespace ARM_MB { } } } // namespace ARM_MB -} // end namespace llvm; -// Note that the following auto-generated files only defined enum types, and -// so are safe to include here. +/// getARMRegisterNumbering - Given the enum value for some register, e.g. +/// ARM::LR, return the number that it corresponds to (e.g. 14). +inline static unsigned getARMRegisterNumbering(unsigned Reg) { + using namespace ARM; + switch (Reg) { + default: + llvm_unreachable("Unknown ARM register!"); + case R0: case S0: case D0: case Q0: return 0; + case R1: case S1: case D1: case Q1: return 1; + case R2: case S2: case D2: case Q2: return 2; + case R3: case S3: case D3: case Q3: return 3; + case R4: case S4: case D4: case Q4: return 4; + case R5: case S5: case D5: case Q5: return 5; + case R6: case S6: case D6: case Q6: return 6; + case R7: case S7: case D7: case Q7: return 7; + case R8: case S8: case D8: case Q8: return 8; + case R9: case S9: case D9: case Q9: return 9; + case R10: case S10: case D10: case Q10: return 10; + case R11: case S11: case D11: case Q11: return 11; + case R12: case S12: case D12: case Q12: return 12; + case SP: case S13: case D13: case Q13: return 13; + case LR: case S14: case D14: case Q14: return 14; + case PC: case S15: case D15: case Q15: return 15; -// Defines symbolic names for ARM registers. This defines a mapping from -// register name to register number. -// -#include "ARMGenRegisterNames.inc" + case S16: case D16: return 16; + case S17: case D17: return 17; + case S18: case D18: return 18; + case S19: case D19: return 19; + case S20: case D20: return 20; + case S21: case D21: return 21; + case S22: case D22: return 22; + case S23: case D23: return 23; + case S24: case D24: return 24; + case S25: case D25: return 25; + case S26: case D26: return 26; + case S27: case D27: return 27; + case S28: case D28: return 28; + case S29: case D29: return 29; + case S30: case D30: return 30; + case S31: case D31: return 31; + } +} -// Defines symbolic names for the ARM instructions. -// -#include "ARMGenInstrNames.inc" +} // end namespace llvm; #endif |
