diff options
Diffstat (limited to 'llvm/lib/Target/ARM/ARM.td')
| -rw-r--r-- | llvm/lib/Target/ARM/ARM.td | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/llvm/lib/Target/ARM/ARM.td b/llvm/lib/Target/ARM/ARM.td index 2e62a079041..8f69c14d792 100644 --- a/llvm/lib/Target/ARM/ARM.td +++ b/llvm/lib/Target/ARM/ARM.td @@ -194,6 +194,10 @@ def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg", "SlowLoadDSubregister", "true", "Loading into D subregs is slow">; +def FeatureUseWideStrideVFP : SubtargetFeature<"wide-stride-vfp", + "UseWideStrideVFP", "true", + "Use a wide stride when allocating VFP registers">; + // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD. def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs", "DontWidenVMOVS", "true", @@ -865,6 +869,7 @@ def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift, FeatureHasRetAddrStack, FeatureNEONForFP, FeatureVFP4, + FeatureUseWideStrideVFP, FeatureMP, FeatureHWDivThumb, FeatureHWDivARM, @@ -1018,24 +1023,28 @@ def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift, FeatureNoPostRASched]>; def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1, + FeatureUseWideStrideVFP, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1, + FeatureUseWideStrideVFP, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynosM1, + FeatureUseWideStrideVFP, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, FeatureCRC]>; def : ProcNoItin<"exynos-m4", [ARMv8a, ProcExynosM1, + FeatureUseWideStrideVFP, FeatureHWDivThumb, FeatureHWDivARM, FeatureCrypto, |
