diff options
Diffstat (limited to 'llvm/lib/Target/ARC/ARCInstrInfo.td')
| -rw-r--r-- | llvm/lib/Target/ARC/ARCInstrInfo.td | 36 |
1 files changed, 32 insertions, 4 deletions
diff --git a/llvm/lib/Target/ARC/ARCInstrInfo.td b/llvm/lib/Target/ARC/ARCInstrInfo.td index edd853fe150..b0306b15d9c 100644 --- a/llvm/lib/Target/ARC/ARCInstrInfo.td +++ b/llvm/lib/Target/ARC/ARCInstrInfo.td @@ -125,18 +125,36 @@ multiclass ArcBinaryInst<bits<5> major, bits<6> mincode, (ins GPR32:$B, GPR32:$C), !strconcat(opasm, "\t$A, $B, $C"), []>; + def _f_rrr : F32_DOP_RR<major, mincode, 1, (outs GPR32:$A), + (ins GPR32:$B, GPR32:$C), + !strconcat(opasm, ".f\t$A, $B, $C"), + []> + { let Defs = [STATUS32]; } // 2 register with unsigned 6-bit immediate variant. def _rru6 : F32_DOP_RU6<major, mincode, 0, (outs GPR32:$A), (ins GPR32:$B, immU6:$U6), !strconcat(opasm, "\t$A, $B, $U6"), []>; + def _f_rru6 : F32_DOP_RU6<major, mincode, 1, (outs GPR32:$A), + (ins GPR32:$B, immU6:$U6), + !strconcat(opasm, ".f\t$A, $B, $U6"), + []> + { let Defs = [STATUS32]; } + // 2 register with 32-bit immediate variant. def _rrlimm : F32_DOP_RLIMM<major, mincode, 0, - (outs GPR32:$A), - (ins GPR32:$B, i32imm:$LImm), - !strconcat(opasm, "\t$A, $B, $LImm"), - []>; + (outs GPR32:$A), + (ins GPR32:$B, i32imm:$LImm), + !strconcat(opasm, "\t$A, $B, $LImm"), + []>; + def _f_rrlimm : F32_DOP_RLIMM<major, mincode, 1, + (outs GPR32:$A), + (ins GPR32:$B, i32imm:$LImm), + !strconcat(opasm, ".f\t$A, $B, $LImm"), + []> + { let Defs = [STATUS32]; } + // 2 matched-register with signed 12-bit immediate variant (add r0, r0, -1). def _rrs12 : F32_DOP_RS12<major, mincode, 0, (outs GPR32:$B), @@ -144,6 +162,12 @@ multiclass ArcBinaryInst<bits<5> major, bits<6> mincode, !strconcat(opasm, "\t$B, $in, $S12"), []> { let Constraints = "$B = $in"; } + def _f_rrs12 : F32_DOP_RS12<major, mincode, 1, + (outs GPR32:$B), + (ins GPR32:$in, immS<12>:$S12), + !strconcat(opasm, ".f\t$B, $in, $S12"), + []> + { let Constraints = "$B = $in"; let Defs = [STATUS32]; } } // Special multivariant GEN4 DOP format instruction that take 2 registers. @@ -168,6 +192,10 @@ multiclass ArcUnaryInst<bits<5> major, bits<6> subop, string opasm> { def _rr : F32_SOP_RR<major, subop, 0, (outs GPR32:$B), (ins GPR32:$C), !strconcat(opasm, "\t$B, $C"), []>; + + def _f_rr : F32_SOP_RR<major, subop, 1, (outs GPR32:$B), (ins GPR32:$C), + !strconcat(opasm, ".f\t$B, $C"), []> + { let Defs = [STATUS32]; } } |
