diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp | 4 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFixControlFlowLiveIntervals.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInstructions.td | 5 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIIntrinsics.td | 1 | ||||
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 19 |
7 files changed, 32 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp index 68cec8ca63f..5f182c5304c 100644 --- a/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SIAnnotateControlFlow.cpp @@ -37,6 +37,7 @@ typedef SmallVector<StackEntry, 16> StackVector; // Intrinsic names the control flow is annotated with static const char *const IfIntrinsic = "llvm.amdgcn.if"; static const char *const ElseIntrinsic = "llvm.amdgcn.else"; +static const char *const BreakIntrinsic = "llvm.amdgcn.break"; static const char *const IfBreakIntrinsic = "llvm.amdgcn.if.break"; static const char *const ElseBreakIntrinsic = "llvm.amdgcn.else.break"; static const char *const LoopIntrinsic = "llvm.amdgcn.loop"; @@ -145,6 +146,9 @@ bool SIAnnotateControlFlow::doInitialization(Module &M) { Else = M.getOrInsertFunction( ElseIntrinsic, ReturnStruct, Int64, (Type *)nullptr); + Break = M.getOrInsertFunction( + BreakIntrinsic, Int64, Int64, (Type *)nullptr); + IfBreak = M.getOrInsertFunction( IfBreakIntrinsic, Int64, Boolean, Int64, (Type *)nullptr); diff --git a/llvm/lib/Target/AMDGPU/SIFixControlFlowLiveIntervals.cpp b/llvm/lib/Target/AMDGPU/SIFixControlFlowLiveIntervals.cpp index a50e07c615d..636750dcfba 100644 --- a/llvm/lib/Target/AMDGPU/SIFixControlFlowLiveIntervals.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixControlFlowLiveIntervals.cpp @@ -72,6 +72,7 @@ bool SIFixControlFlowLiveIntervals::runOnMachineFunction(MachineFunction &MF) { switch (MI.getOpcode()) { case AMDGPU::SI_IF: case AMDGPU::SI_ELSE: + case AMDGPU::SI_BREAK: case AMDGPU::SI_IF_BREAK: case AMDGPU::SI_ELSE_BREAK: case AMDGPU::SI_END_CF: { diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index c9693ea4f05..9e0086b7908 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -324,6 +324,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { assert(DefInstr); switch(DefInstr->getOpcode()) { + case AMDGPU::SI_BREAK: case AMDGPU::SI_IF_BREAK: case AMDGPU::SI_ELSE_BREAK: // If we see a PHI instruction that defines an SGPR, then that PHI diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 29c40851ea9..4455e9cb170 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -1261,6 +1261,7 @@ bool SITargetLowering::isCFIntrinsic(const SDNode *Intr) const { default: return false; case AMDGPUIntrinsic::amdgcn_if: case AMDGPUIntrinsic::amdgcn_else: + case AMDGPUIntrinsic::amdgcn_break: case AMDGPUIntrinsic::amdgcn_if_break: case AMDGPUIntrinsic::amdgcn_else_break: case AMDGPUIntrinsic::amdgcn_loop: diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index 3eebd1bad27..6ded07c17d9 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -1958,6 +1958,11 @@ def SI_LOOP : InstSI < } // End isBranch = 1, isTerminator = 1 +def SI_BREAK : InstSI < + (outs SReg_64:$dst), (ins SReg_64:$src), "", + [(set i64:$dst, (int_amdgcn_break i64:$src))] +>; + def SI_IF_BREAK : InstSI < (outs SReg_64:$dst), (ins SReg_64:$vcc, SReg_64:$src), "", [(set i64:$dst, (int_amdgcn_if_break i1:$vcc, i64:$src))] diff --git a/llvm/lib/Target/AMDGPU/SIIntrinsics.td b/llvm/lib/Target/AMDGPU/SIIntrinsics.td index f51944fa401..a9b7c39096e 100644 --- a/llvm/lib/Target/AMDGPU/SIIntrinsics.td +++ b/llvm/lib/Target/AMDGPU/SIIntrinsics.td @@ -181,6 +181,7 @@ let TargetPrefix = "amdgcn", isTarget = 1 in { def int_amdgcn_if : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_empty_ty], []>; def int_amdgcn_else : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_empty_ty], []>; + def int_amdgcn_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty], []>; def int_amdgcn_if_break : Intrinsic<[llvm_i64_ty], [llvm_i1_ty, llvm_i64_ty], []>; def int_amdgcn_else_break : Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty], []>; def int_amdgcn_loop : Intrinsic<[], [llvm_i64_ty, llvm_empty_ty], []>; diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp index 1ba14cd2d1c..3d6fc9eeba7 100644 --- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp @@ -80,6 +80,7 @@ private: void If(MachineInstr &MI); void Else(MachineInstr &MI, bool ExecModified); + void Break(MachineInstr &MI); void IfBreak(MachineInstr &MI); void ElseBreak(MachineInstr &MI); void Loop(MachineInstr &MI); @@ -276,6 +277,20 @@ void SILowerControlFlow::Else(MachineInstr &MI, bool ExecModified) { MI.eraseFromParent(); } +void SILowerControlFlow::Break(MachineInstr &MI) { + MachineBasicBlock &MBB = *MI.getParent(); + DebugLoc DL = MI.getDebugLoc(); + + unsigned Dst = MI.getOperand(0).getReg(); + unsigned Src = MI.getOperand(1).getReg(); + + BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_OR_B64), Dst) + .addReg(AMDGPU::EXEC) + .addReg(Src); + + MI.eraseFromParent(); +} + void SILowerControlFlow::IfBreak(MachineInstr &MI) { MachineBasicBlock &MBB = *MI.getParent(); DebugLoc DL = MI.getDebugLoc(); @@ -661,6 +676,10 @@ bool SILowerControlFlow::runOnMachineFunction(MachineFunction &MF) { Else(MI, ExecModified); break; + case AMDGPU::SI_BREAK: + Break(MI); + break; + case AMDGPU::SI_IF_BREAK: IfBreak(MI); break; |
