diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SMInstructions.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SMInstructions.td | 23 |
1 files changed, 22 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td index db9cc72a9d0..797586bbb54 100644 --- a/llvm/lib/Target/AMDGPU/SMInstructions.td +++ b/llvm/lib/Target/AMDGPU/SMInstructions.td @@ -682,7 +682,22 @@ def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>; // Scalar Memory Patterns //===----------------------------------------------------------------------===// -def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{ return isUniformLoad(N);}]>; +def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{ return isUniformLoad(N);}]> { + let GISelPredicateCode = [{ + if (!MI.hasOneMemOperand()) + return false; + if (!isInstrUniform(MI)) + return false; + + // FIXME: We should probably be caching this. + SmallVector<GEPInfo, 4> AddrInfo; + getAddrModeInfo(MI, MRI, AddrInfo); + + if (hasVgprParts(AddrInfo)) + return false; + return true; + }]; +} def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">; def SMRDImm32 : ComplexPattern<i64, 2, "SelectSMRDImm32">; @@ -710,6 +725,12 @@ multiclass SMRD_Pattern <string Instr, ValueType vt> { (smrd_load (SMRDSgpr i64:$sbase, i32:$offset)), (vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset, 0)) >; + + // 4. No offset + def : GCNPat < + (vt (smrd_load (i64 SReg_64:$sbase))), + (vt (!cast<SM_Pseudo>(Instr#"_IMM") i64:$sbase, 0, 0)) + >; } multiclass SMLoad_Pattern <string Instr, ValueType vt> { |
