diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 54 |
1 files changed, 53 insertions, 1 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 8bb8ea71332..f7d61725110 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -324,6 +324,57 @@ static yaml::StringValue regToString(unsigned Reg, return Dest; } +static Optional<yaml::SIArgumentInfo> +convertArgumentInfo(const AMDGPUFunctionArgInfo &ArgInfo, + const TargetRegisterInfo &TRI) { + yaml::SIArgumentInfo AI; + + auto convertArg = [&](Optional<yaml::SIArgument> &A, + const ArgDescriptor &Arg) { + if (!Arg) + return false; + + // Create a register or stack argument. + yaml::SIArgument SA = yaml::SIArgument::createArgument(Arg.isRegister()); + if (Arg.isRegister()) { + raw_string_ostream OS(SA.RegisterName.Value); + OS << printReg(Arg.getRegister(), &TRI); + } else + SA.StackOffset = Arg.getStackOffset(); + // Check and update the optional mask. + if (Arg.isMasked()) + SA.Mask = Arg.getMask(); + + A = SA; + return true; + }; + + bool Any = false; + Any |= convertArg(AI.PrivateSegmentBuffer, ArgInfo.PrivateSegmentBuffer); + Any |= convertArg(AI.DispatchPtr, ArgInfo.DispatchPtr); + Any |= convertArg(AI.QueuePtr, ArgInfo.QueuePtr); + Any |= convertArg(AI.KernargSegmentPtr, ArgInfo.KernargSegmentPtr); + Any |= convertArg(AI.DispatchID, ArgInfo.DispatchID); + Any |= convertArg(AI.FlatScratchInit, ArgInfo.FlatScratchInit); + Any |= convertArg(AI.PrivateSegmentSize, ArgInfo.PrivateSegmentSize); + Any |= convertArg(AI.WorkGroupIDX, ArgInfo.WorkGroupIDX); + Any |= convertArg(AI.WorkGroupIDY, ArgInfo.WorkGroupIDY); + Any |= convertArg(AI.WorkGroupIDZ, ArgInfo.WorkGroupIDZ); + Any |= convertArg(AI.WorkGroupInfo, ArgInfo.WorkGroupInfo); + Any |= convertArg(AI.PrivateSegmentWaveByteOffset, + ArgInfo.PrivateSegmentWaveByteOffset); + Any |= convertArg(AI.ImplicitArgPtr, ArgInfo.ImplicitArgPtr); + Any |= convertArg(AI.ImplicitBufferPtr, ArgInfo.ImplicitBufferPtr); + Any |= convertArg(AI.WorkItemIDX, ArgInfo.WorkItemIDX); + Any |= convertArg(AI.WorkItemIDY, ArgInfo.WorkItemIDY); + Any |= convertArg(AI.WorkItemIDZ, ArgInfo.WorkItemIDZ); + + if (Any) + return AI; + + return None; +} + yaml::SIMachineFunctionInfo::SIMachineFunctionInfo( const llvm::SIMachineFunctionInfo& MFI, const TargetRegisterInfo &TRI) @@ -337,7 +388,8 @@ yaml::SIMachineFunctionInfo::SIMachineFunctionInfo( ScratchRSrcReg(regToString(MFI.getScratchRSrcReg(), TRI)), ScratchWaveOffsetReg(regToString(MFI.getScratchWaveOffsetReg(), TRI)), FrameOffsetReg(regToString(MFI.getFrameOffsetReg(), TRI)), - StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)) {} + StackPtrOffsetReg(regToString(MFI.getStackPtrOffsetReg(), TRI)), + ArgInfo(convertArgumentInfo(MFI.getArgInfo(), TRI)) {} void yaml::SIMachineFunctionInfo::mappingImpl(yaml::IO &YamlIO) { MappingTraits<SIMachineFunctionInfo>::mapping(YamlIO, *this); |
