1 files changed, 30 insertions, 15 deletions

diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index 0dbe080bf6b..b2df4e0e681 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -1,4 +1,4 @@
-//===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===//
+//===- SIInstrInfo.h - SI Instruction Info Interface ------------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -12,17 +12,33 @@
 //
 //===----------------------------------------------------------------------===//
 
-
 #ifndef LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
 #define LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H
 
 #include "AMDGPUInstrInfo.h"
 #include "SIDefines.h"
 #include "SIRegisterInfo.h"
+#include "Utils/AMDGPUBaseInfo.h"
+#include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SetVector.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
+#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineInstr.h"
+#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineOperand.h"
+#include "llvm/MC/MCInstrDesc.h"
+#include "llvm/Support/Compiler.h"
+#include <cassert>
+#include <cstdint>
 
 namespace llvm {
 
+class APInt;
+class MachineRegisterInfo;
+class RegScavenger;
+class SISubtarget;
+class TargetRegisterClass;
+
 class SIInstrInfo final : public AMDGPUInstrInfo {
 private:
   const SIRegisterInfo RI;
@@ -39,7 +55,7 @@ private:
     EXECZ = 3
   };
 
-  typedef SmallSetVector<MachineInstr *, 32> SetVectorType;
+  using SetVectorType = SmallSetVector<MachineInstr *, 32>;
 
   static unsigned getBranchOpcode(BranchPredicate Cond);
   static BranchPredicate getBranchPredicate(unsigned Opcode);
@@ -76,9 +92,8 @@ private:
                       MachineRegisterInfo &MRI,
                       MachineInstr &Inst) const;
 
-  void addUsersToMoveToVALUWorklist(
-    unsigned Reg, MachineRegisterInfo &MRI,
-    SetVectorType &Worklist) const;
+  void addUsersToMoveToVALUWorklist(unsigned Reg, MachineRegisterInfo &MRI,
+                                    SetVectorType &Worklist) const;
 
   void
   addSCCDefUsersToVALUWorklist(MachineInstr &SCCDefInst,
@@ -101,7 +116,6 @@ protected:
                                        unsigned OpIdx1) const override;
 
 public:
-
   enum TargetOperandFlags {
     MO_MASK = 0x7,
 
@@ -120,7 +134,7 @@ public:
     MO_REL32_HI = 5
   };
 
-  explicit SIInstrInfo(const SISubtarget &);
+  explicit SIInstrInfo(const SISubtarget &ST);
 
   const SIRegisterInfo &getRegisterInfo() const {
     return RI;
@@ -159,7 +173,7 @@ public:
 
   unsigned insertNE(MachineBasicBlock *MBB,
                     MachineBasicBlock::iterator I, const DebugLoc &DL,
-                    unsigned SrcReg, int Value)  const;
+                    unsigned SrcReg, int Value) const;
 
   unsigned insertEQ(MachineBasicBlock *MBB,
                     MachineBasicBlock::iterator I, const DebugLoc &DL,
@@ -228,7 +242,6 @@ public:
   bool reverseBranchCondition(
     SmallVectorImpl<MachineOperand> &Cond) const override;
 
-
   bool canInsertSelect(const MachineBasicBlock &MBB,
                        ArrayRef<MachineOperand> Cond,
                        unsigned TrueReg, unsigned FalseReg,
@@ -827,6 +840,7 @@ public:
 };
 
 namespace AMDGPU {
+
   LLVM_READONLY
   int getVOPe64(uint16_t Opcode);
 
@@ -867,7 +881,8 @@ namespace AMDGPU {
     TF_LONG_BRANCH_FORWARD = 1 << 0,
     TF_LONG_BRANCH_BACKWARD = 1 << 1
   };
-} // End namespace AMDGPU
+
+} // end namespace AMDGPU
 
 namespace SI {
 namespace KernelInputOffsets {
@@ -885,9 +900,9 @@ enum Offsets {
   LOCAL_SIZE_Z = 32
 };
 
-} // End namespace KernelInputOffsets
-} // End namespace SI
+} // end namespace KernelInputOffsets
+} // end namespace SI
 
-} // End namespace llvm
+} // end namespace llvm
 
-#endif
+#endif // LLVM_LIB_TARGET_AMDGPU_SIINSTRINFO_H