diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/SIInsertWaits.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/SIInsertWaits.cpp | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp index 2379b1fcf6a..b47c09bc9b6 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaits.cpp @@ -140,7 +140,7 @@ FunctionPass *llvm::createSIInsertWaits(TargetMachine &tm) { Counters SIInsertWaits::getHwCounts(MachineInstr &MI) { uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags; - Counters Result; + Counters Result = { { 0, 0, 0 } }; Result.Named.VM = !!(TSFlags & SIInstrFlags::VM_CNT); @@ -153,13 +153,21 @@ Counters SIInsertWaits::getHwCounts(MachineInstr &MI) { if (TII->isSMRD(MI.getOpcode())) { - MachineOperand &Op = MI.getOperand(0); - assert(Op.isReg() && "First LGKM operand must be a register!"); + if (MI.getNumOperands() != 0) { + MachineOperand &Op = MI.getOperand(0); + assert(Op.isReg() && "First LGKM operand must be a register!"); - unsigned Reg = Op.getReg(); - unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); - Result.Named.LGKM = Size > 4 ? 2 : 1; + unsigned Reg = Op.getReg(); + // XXX - What if this is a write into a super register? + unsigned Size = TRI->getMinimalPhysRegClass(Reg)->getSize(); + Result.Named.LGKM = Size > 4 ? 2 : 1; + } else { + // s_dcache_inv etc. do not have a a destination register. Assume we + // want a wait on these. + // XXX - What is the right value? + Result.Named.LGKM = 1; + } } else { // DS Result.Named.LGKM = 1; |
