diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 76 |
1 files changed, 76 insertions, 0 deletions
diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index 114f98cbfaa..114f46ef270 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -451,6 +451,12 @@ void AMDGPUInstPrinter::printVOPDst(const MCInst *MI, unsigned OpNo, case AMDGPU::V_ADD_CO_CI_U32_sdwa_gfx10: case AMDGPU::V_SUB_CO_CI_U32_sdwa_gfx10: case AMDGPU::V_SUBREV_CO_CI_U32_sdwa_gfx10: + case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: + case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: + case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: + case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: + case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: + case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: printDefaultVccOperand(1, STI, O); break; } @@ -681,6 +687,12 @@ void AMDGPUInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, case AMDGPU::V_ADD_CO_CI_U32_e32_gfx10: case AMDGPU::V_SUB_CO_CI_U32_e32_gfx10: case AMDGPU::V_SUBREV_CO_CI_U32_e32_gfx10: + case AMDGPU::V_ADD_CO_CI_U32_dpp_gfx10: + case AMDGPU::V_SUB_CO_CI_U32_dpp_gfx10: + case AMDGPU::V_SUBREV_CO_CI_U32_dpp_gfx10: + case AMDGPU::V_ADD_CO_CI_U32_dpp8_gfx10: + case AMDGPU::V_SUB_CO_CI_U32_dpp8_gfx10: + case AMDGPU::V_SUBREV_CO_CI_U32_dpp8_gfx10: case AMDGPU::V_CNDMASK_B32_e32_gfx6_gfx7: case AMDGPU::V_CNDMASK_B32_e32_vi: @@ -750,6 +762,20 @@ void AMDGPUInstPrinter::printOperandAndIntInputMods(const MCInst *MI, } } +void AMDGPUInstPrinter::printDPP8(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + if (!AMDGPU::isGFX10(STI)) + llvm_unreachable("dpp8 is not supported on ASICs earlier than GFX10"); + + unsigned Imm = MI->getOperand(OpNo).getImm(); + O << " dpp8:[" << formatDec(Imm & 0x7); + for (size_t i = 1; i < 8; ++i) { + O << ',' << formatDec((Imm >> (3 * i)) & 0x7); + } + O << ']'; +} + void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { @@ -775,21 +801,61 @@ void AMDGPUInstPrinter::printDPPCtrl(const MCInst *MI, unsigned OpNo, O << " row_ror:"; printU4ImmDecOperand(MI, OpNo, O); } else if (Imm == DppCtrl::WAVE_SHL1) { + if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + O << " /* wave_shl is not supported starting from GFX10 */"; + return; + } O << " wave_shl:1"; } else if (Imm == DppCtrl::WAVE_ROL1) { + if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + O << " /* wave_rol is not supported starting from GFX10 */"; + return; + } O << " wave_rol:1"; } else if (Imm == DppCtrl::WAVE_SHR1) { + if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + O << " /* wave_shr is not supported starting from GFX10 */"; + return; + } O << " wave_shr:1"; } else if (Imm == DppCtrl::WAVE_ROR1) { + if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + O << " /* wave_ror is not supported starting from GFX10 */"; + return; + } O << " wave_ror:1"; } else if (Imm == DppCtrl::ROW_MIRROR) { O << " row_mirror"; } else if (Imm == DppCtrl::ROW_HALF_MIRROR) { O << " row_half_mirror"; } else if (Imm == DppCtrl::BCAST15) { + if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + O << " /* row_bcast is not supported starting from GFX10 */"; + return; + } O << " row_bcast:15"; } else if (Imm == DppCtrl::BCAST31) { + if (!AMDGPU::isVI(STI) && !AMDGPU::isGFX9(STI)) { + O << " /* row_bcast is not supported starting from GFX10 */"; + return; + } O << " row_bcast:31"; + } else if ((Imm >= DppCtrl::ROW_SHARE_FIRST) && + (Imm <= DppCtrl::ROW_SHARE_LAST)) { + if (!AMDGPU::isGFX10(STI)) { + O << " /* row_share is not supported on ASICs earlier than GFX10 */"; + return; + } + O << " row_share:"; + printU4ImmDecOperand(MI, OpNo, O); + } else if ((Imm >= DppCtrl::ROW_XMASK_FIRST) && + (Imm <= DppCtrl::ROW_XMASK_LAST)) { + if (!AMDGPU::isGFX10(STI)) { + O << " /* row_xmask is not supported on ASICs earlier than GFX10 */"; + return; + } + O << "row_xmask:"; + printU4ImmDecOperand(MI, OpNo, O); } else { O << " /* Invalid dpp_ctrl value */"; } @@ -818,6 +884,16 @@ void AMDGPUInstPrinter::printBoundCtrl(const MCInst *MI, unsigned OpNo, } } +void AMDGPUInstPrinter::printFI(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + using namespace llvm::AMDGPU::DPP; + unsigned Imm = MI->getOperand(OpNo).getImm(); + if (Imm == DPP_FI_1 || Imm == DPP8_FI_1) { + O << " fi:1"; + } +} + void AMDGPUInstPrinter::printSDWASel(const MCInst *MI, unsigned OpNo, raw_ostream &O) { using namespace llvm::AMDGPU::SDWA; |
