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-rw-r--r--llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h13
1 files changed, 9 insertions, 4 deletions
diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
index 9045b7fbd59..c8b2f1ff239 100644
--- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
+++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
@@ -18,7 +18,11 @@
#include "llvm/ADT/ArrayRef.h"
#include "llvm/MC/MCDisassembler/MCDisassembler.h"
+#include "llvm/MC/MCDisassembler/MCRelocationInfo.h"
#include "llvm/MC/MCDisassembler/MCSymbolizer.h"
+#include <cstdint>
+#include <algorithm>
+#include <memory>
namespace llvm {
@@ -40,7 +44,7 @@ public:
AMDGPUDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) :
MCDisassembler(STI, Ctx) {}
- ~AMDGPUDisassembler() {}
+ ~AMDGPUDisassembler() override = default;
DecodeStatus getInstruction(MCInst &MI, uint64_t &Size,
ArrayRef<uint8_t> Bytes, uint64_t Address,
@@ -52,7 +56,7 @@ public:
MCOperand createRegOperand(unsigned RegClassID, unsigned Val) const;
MCOperand createSRegOperand(unsigned SRegClassID, unsigned Val) const;
- MCOperand errOperand(unsigned V, const llvm::Twine& ErrMsg) const;
+ MCOperand errOperand(unsigned V, const Twine& ErrMsg) const;
DecodeStatus tryDecodeInst(const uint8_t* Table,
MCInst &MI,
@@ -82,6 +86,7 @@ public:
OPW_LAST_,
OPW_FIRST_ = OPW32
};
+
unsigned getVgprClassId(const OpWidthTy Width) const;
unsigned getSgprClassId(const OpWidthTy Width) const;
unsigned getTtmpClassId(const OpWidthTy Width) const;
@@ -118,6 +123,6 @@ public:
uint64_t Address) override;
};
-} // namespace llvm
+} // end namespace llvm
-#endif //LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
+#endif // LLVM_LIB_TARGET_AMDGPU_DISASSEMBLER_AMDGPUDISASSEMBLER_H
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