diff options
Diffstat (limited to 'llvm/lib/Target/AMDGPU/BUFInstructions.td')
| -rw-r--r-- | llvm/lib/Target/AMDGPU/BUFInstructions.td | 31 |
1 files changed, 16 insertions, 15 deletions
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td index 030fd459b0f..5e50e73a26a 100644 --- a/llvm/lib/Target/AMDGPU/BUFInstructions.td +++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td @@ -943,7 +943,7 @@ let SubtargetPredicate = isVI in { def BUFFER_STORE_LDS_DWORD : MUBUF_Pseudo_Store_Lds <"buffer_store_lds_dword">; } -let SubtargetPredicate = isSI in { // isn't on CI & VI +let SubtargetPredicate = isGFX6 in { // isn't on CI & VI /* defm BUFFER_ATOMIC_RSUB : MUBUF_Pseudo_Atomics <"buffer_atomic_rsub">; defm BUFFER_ATOMIC_FCMPSWAP : MUBUF_Pseudo_Atomics <"buffer_atomic_fcmpswap">; @@ -1040,7 +1040,7 @@ let SubtargetPredicate = HasPackedD16VMem, D16Buf = 1 in { defm TBUFFER_STORE_FORMAT_D16_XYZW : MTBUF_Pseudo_Stores <"tbuffer_store_format_d16_xyzw", VReg_64>; } // End HasPackedD16VMem. -let SubtargetPredicate = isCIVI in { +let SubtargetPredicate = isGFX7Plus in { //===----------------------------------------------------------------------===// // Instruction definitions for CI and newer. @@ -1049,7 +1049,7 @@ let SubtargetPredicate = isCIVI in { def BUFFER_WBINVL1_VOL : MUBUF_Invalidate <"buffer_wbinvl1_vol", int_amdgcn_buffer_wbinvl1_vol>; -} // End let SubtargetPredicate = isCIVI +} // End let SubtargetPredicate = isGFX7Plus //===----------------------------------------------------------------------===// // MUBUF Patterns @@ -1340,7 +1340,7 @@ multiclass MUBUFLoad_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Ins >; } -let SubtargetPredicate = isSICI in { +let SubtargetPredicate = isGFX6GFX7 in { def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SBYTE_ADDR64, i32, sextloadi8_constant>; def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_UBYTE_ADDR64, i32, az_extloadi8_constant>; def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_SSHORT_ADDR64, i32, sextloadi16_constant>; @@ -1348,7 +1348,7 @@ def : MUBUFLoad_PatternADDR64 <BUFFER_LOAD_USHORT_ADDR64, i32, az_extloadi16_con defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORD_ADDR64, BUFFER_LOAD_DWORD_OFFSET, i32, mubuf_load_atomic>; defm : MUBUFLoad_Atomic_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, BUFFER_LOAD_DWORDX2_OFFSET, i64, mubuf_load_atomic>; -} // End SubtargetPredicate = isSICI +} // End SubtargetPredicate = isGFX6GFX7 multiclass MUBUFLoad_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt, PatFrag ld> { @@ -1428,6 +1428,7 @@ defm : MUBUFScratchLoadPat_D16<BUFFER_LOAD_SHORT_D16_OFFEN, BUFFER_LOAD_SHORT_D1 defm : MUBUFScratchLoadPat_D16<BUFFER_LOAD_UBYTE_D16_OFFEN, BUFFER_LOAD_UBYTE_D16_OFFSET, v2f16, az_extloadi8_d16_lo_private>; defm : MUBUFScratchLoadPat_D16<BUFFER_LOAD_SBYTE_D16_OFFEN, BUFFER_LOAD_SBYTE_D16_OFFSET, v2f16, sextloadi8_d16_lo_private>; } + multiclass MUBUFStore_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo Instr_OFFSET, ValueType vt, PatFrag atomic_st> { // Store follows atomic op convention so address is forst @@ -1442,10 +1443,10 @@ multiclass MUBUFStore_Atomic_Pattern <MUBUF_Pseudo Instr_ADDR64, MUBUF_Pseudo In (Instr_OFFSET $val, $rsrc, $soffset, (as_i16imm $offset), 0, 0, 0) >; } -let SubtargetPredicate = isSICI in { +let SubtargetPredicate = isGFX6GFX7 in { defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORD_ADDR64, BUFFER_STORE_DWORD_OFFSET, i32, store_atomic_global>; defm : MUBUFStore_Atomic_Pattern <BUFFER_STORE_DWORDX2_ADDR64, BUFFER_STORE_DWORDX2_OFFSET, i64, store_atomic_global>; -} // End Predicates = isSICI +} // End Predicates = isGFX6GFX7 multiclass MUBUFStore_Pattern <MUBUF_Pseudo Instr_OFFSET, ValueType vt, @@ -1621,19 +1622,19 @@ let SubtargetPredicate = HasPackedD16VMem in { } // End HasPackedD16VMem. //===----------------------------------------------------------------------===// -// Target instructions, move to the appropriate target TD file +// Target-specific instruction encodings. //===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===// -// SI +// Base ENC_MUBUF for GFX6, GFX7. //===----------------------------------------------------------------------===// class MUBUF_Real_si <bits<7> op, MUBUF_Pseudo ps> : MUBUF_Real<op, ps>, Enc64, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> { - let AssemblerPredicate=isSICI; - let DecoderNamespace="SICI"; + let AssemblerPredicate=isGFX6GFX7; + let DecoderNamespace="GFX6GFX7"; let Inst{11-0} = !if(ps.has_offset, offset, ?); let Inst{12} = ps.offen; @@ -1759,8 +1760,8 @@ class MTBUF_Real_si <bits<3> op, MTBUF_Pseudo ps> : MTBUF_Real<ps>, Enc64, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI> { - let AssemblerPredicate=isSICI; - let DecoderNamespace="SICI"; + let AssemblerPredicate=isGFX6GFX7; + let DecoderNamespace="GFX6GFX7"; let Inst{11-0} = !if(ps.has_offset, offset, ?); let Inst{12} = ps.offen; @@ -1804,14 +1805,14 @@ defm TBUFFER_STORE_FORMAT_XYZW : MTBUF_Real_AllAddr_si <7>; class MUBUF_Real_ci <bits<7> op, MUBUF_Pseudo ps> : MUBUF_Real_si<op, ps> { let AssemblerPredicate=isCIOnly; - let DecoderNamespace="CI"; + let DecoderNamespace="GFX7"; } def BUFFER_WBINVL1_VOL_ci : MUBUF_Real_ci <0x70, BUFFER_WBINVL1_VOL>; //===----------------------------------------------------------------------===// -// VI +// GFX8, GFX9 (VI). //===----------------------------------------------------------------------===// class MUBUF_Real_vi <bits<7> op, MUBUF_Pseudo ps> : |
