diff options
Diffstat (limited to 'llvm/lib/Target/AArch64')
6 files changed, 31 insertions, 43 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp index 17aae86e146..904cb53cb8e 100644 --- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -191,8 +191,8 @@ public: /// runOnMachineFunction - Initialize per-function data structures. void runOnMachineFunction(MachineFunction &MF) { this->MF = &MF; - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); MRI = &MF.getRegInfo(); } @@ -891,8 +891,8 @@ bool AArch64ConditionalCompares::tryConvert(MachineBasicBlock *MBB) { bool AArch64ConditionalCompares::runOnMachineFunction(MachineFunction &MF) { DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n" << "********** Function: " << MF.getName() << '\n'); - TII = MF.getTarget().getSubtargetImpl()->getInstrInfo(); - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = MF.getSubtarget().getInstrInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); SchedModel = MF.getTarget().getSubtarget<TargetSubtargetInfo>().getSchedModel(); MRI = &MF.getRegInfo(); diff --git a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp index 0c9b2ae0928..5174c62a916 100644 --- a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp +++ b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp @@ -120,7 +120,7 @@ bool AArch64DeadRegisterDefinitions::processMachineBasicBlock( // Scan the function for instructions that have a dead definition of a // register. Replace that register with the zero register when possible. bool AArch64DeadRegisterDefinitions::runOnMachineFunction(MachineFunction &MF) { - TRI = MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + TRI = MF.getSubtarget().getRegisterInfo(); bool Changed = false; DEBUG(dbgs() << "***** AArch64DeadRegisterDefinitions *****\n"); diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp index 9768de152f9..c850680d4c6 100644 --- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp +++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp @@ -723,8 +723,7 @@ bool AArch64ExpandPseudo::expandMBB(MachineBasicBlock &MBB) { } bool AArch64ExpandPseudo::runOnMachineFunction(MachineFunction &MF) { - TII = static_cast<const AArch64InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); bool Modified = false; for (auto &MBB : MF) diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp index 77b2551f0d2..44903fcb381 100644 --- a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp @@ -86,8 +86,7 @@ bool AArch64FrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); #ifndef NDEBUG - const TargetRegisterInfo *RegInfo = - MF.getTarget().getSubtargetImpl()->getRegisterInfo(); + const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); assert(!RegInfo->needsStackRealignment(MF) && "No stack realignment on AArch64!"); #endif @@ -109,15 +108,14 @@ AArch64FrameLowering::hasReservedCallFrame(const MachineFunction &MF) const { void AArch64FrameLowering::eliminateCallFramePseudoInstr( MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { - const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const AArch64InstrInfo *TII = + static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); DebugLoc DL = I->getDebugLoc(); int Opc = I->getOpcode(); bool IsDestroy = Opc == TII->getCallFrameDestroyOpcode(); uint64_t CalleePopAmount = IsDestroy ? I->getOperand(1).getImm() : 0; - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); if (!TFI->hasReservedCallFrame(MF)) { unsigned Align = getStackAlignment(); @@ -160,8 +158,7 @@ void AArch64FrameLowering::emitCalleeSavedFrameMoves( MachineFrameInfo *MFI = MF.getFrameInfo(); MachineModuleInfo &MMI = MF.getMMI(); const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); - const TargetInstrInfo *TII = - MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); DebugLoc DL = MBB.findDebugLoc(MBBI); // Add callee saved registers to move list. @@ -169,7 +166,7 @@ void AArch64FrameLowering::emitCalleeSavedFrameMoves( if (CSI.empty()) return; - const DataLayout *TD = MF.getTarget().getSubtargetImpl()->getDataLayout(); + const DataLayout *TD = MF.getSubtarget().getDataLayout(); bool HasFP = hasFP(MF); // Calculate amount of bytes used for return address storing. @@ -208,9 +205,8 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const Function *Fn = MF.getFunction(); const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); - const TargetInstrInfo *TII = - MF.getTarget().getSubtargetImpl()->getInstrInfo(); + MF.getSubtarget().getRegisterInfo()); + const TargetInstrInfo *TII = MF.getSubtarget().getInstrInfo(); MachineModuleInfo &MMI = MF.getMMI(); AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); bool needsFrameMoves = MMI.hasDebugInfo() || Fn->needsUnwindTableEntry(); @@ -304,7 +300,7 @@ void AArch64FrameLowering::emitPrologue(MachineFunction &MF) const { TII->copyPhysReg(MBB, MBBI, DL, AArch64::X19, AArch64::SP, false); if (needsFrameMoves) { - const DataLayout *TD = MF.getTarget().getSubtargetImpl()->getDataLayout(); + const DataLayout *TD = MF.getSubtarget().getDataLayout(); const int StackGrowth = -TD->getPointerSize(0); unsigned FramePtr = RegInfo->getFrameRegister(MF); @@ -438,10 +434,10 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); assert(MBBI->isReturn() && "Can only insert epilog into returning blocks"); MachineFrameInfo *MFI = MF.getFrameInfo(); - const AArch64InstrInfo *TII = static_cast<const AArch64InstrInfo *>( - MF.getTarget().getSubtargetImpl()->getInstrInfo()); + const AArch64InstrInfo *TII = + static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo()); const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); DebugLoc DL = MBBI->getDebugLoc(); unsigned RetOpcode = MBBI->getOpcode(); @@ -552,7 +548,7 @@ int AArch64FrameLowering::resolveFrameIndexReference(const MachineFunction &MF, bool PreferFP) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); int FPOffset = MFI->getObjectOffset(FI) + 16; int Offset = MFI->getObjectOffset(FI) + MFI->getStackSize(); @@ -621,8 +617,7 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters( const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const { MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned Count = CSI.size(); DebugLoc DL; assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!"); @@ -698,8 +693,7 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters( const std::vector<CalleeSavedInfo> &CSI, const TargetRegisterInfo *TRI) const { MachineFunction &MF = *MBB.getParent(); - const TargetInstrInfo &TII = - *MF.getTarget().getSubtargetImpl()->getInstrInfo(); + const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); unsigned Count = CSI.size(); DebugLoc DL; assert((Count & 1) == 0 && "Odd number of callee-saved regs to spill!"); @@ -767,7 +761,7 @@ bool AArch64FrameLowering::restoreCalleeSavedRegisters( void AArch64FrameLowering::processFunctionBeforeCalleeSavedScan( MachineFunction &MF, RegScavenger *RS) const { const AArch64RegisterInfo *RegInfo = static_cast<const AArch64RegisterInfo *>( - MF.getTarget().getSubtargetImpl()->getRegisterInfo()); + MF.getSubtarget().getRegisterInfo()); AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); MachineRegisterInfo *MRI = &MF.getRegInfo(); SmallVector<unsigned, 4> UnspilledCSGPRs; diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp index 8c777640339..d734d436add 100644 --- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp @@ -76,8 +76,7 @@ AArch64RegisterInfo::getThisReturnPreservedMask(CallingConv::ID) const { BitVector AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); // FIXME: avoid re-calculating this every time. BitVector Reserved(getNumRegs()); @@ -106,8 +105,7 @@ AArch64RegisterInfo::getReservedRegs(const MachineFunction &MF) const { bool AArch64RegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); switch (Reg) { default: @@ -171,8 +169,7 @@ bool AArch64RegisterInfo::hasBasePointer(const MachineFunction &MF) const { unsigned AArch64RegisterInfo::getFrameRegister(const MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); return TFI->hasFP(MF) ? AArch64::FP : AArch64::SP; } @@ -239,8 +236,7 @@ bool AArch64RegisterInfo::needsFrameBaseReg(MachineInstr *MI, // Note that the incoming offset is based on the SP value at function entry, // so it'll be negative. MachineFunction &MF = *MI->getParent()->getParent(); - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); MachineFrameInfo *MFI = MF.getFrameInfo(); // Estimate an offset from the frame pointer. @@ -330,7 +326,7 @@ void AArch64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, MachineBasicBlock &MBB = *MI.getParent(); MachineFunction &MF = *MBB.getParent(); const AArch64FrameLowering *TFI = static_cast<const AArch64FrameLowering *>( - MF.getTarget().getSubtargetImpl()->getFrameLowering()); + MF.getSubtarget().getFrameLowering()); int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); unsigned FrameReg; @@ -368,8 +364,7 @@ namespace llvm { unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC, MachineFunction &MF) const { - const TargetFrameLowering *TFI = - MF.getTarget().getSubtargetImpl()->getFrameLowering(); + const TargetFrameLowering *TFI = MF.getSubtarget().getFrameLowering(); switch (RC->getID()) { default: diff --git a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp index b09ecb74a71..61370a5387b 100644 --- a/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp +++ b/llvm/lib/Target/AArch64/AArch64StorePairSuppress.cpp @@ -118,9 +118,9 @@ bool AArch64StorePairSuppress::isNarrowFPStore(const MachineInstr &MI) { bool AArch64StorePairSuppress::runOnMachineFunction(MachineFunction &mf) { MF = &mf; - TII = static_cast<const AArch64InstrInfo *>( - MF->getTarget().getSubtargetImpl()->getInstrInfo()); - TRI = MF->getTarget().getSubtargetImpl()->getRegisterInfo(); + TII = + static_cast<const AArch64InstrInfo *>(MF->getSubtarget().getInstrInfo()); + TRI = MF->getSubtarget().getRegisterInfo(); MRI = &MF->getRegInfo(); const TargetSubtargetInfo &ST = MF->getTarget().getSubtarget<TargetSubtargetInfo>(); |
