diff options
Diffstat (limited to 'llvm/lib/Target/AArch64')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64CallLowering.cpp | 111 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64CallLowering.h | 36 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 78 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64ISelLowering.h | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 9 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64Subtarget.h | 3 | ||||
| -rw-r--r-- | llvm/lib/Target/AArch64/CMakeLists.txt | 1 |
7 files changed, 159 insertions, 88 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp new file mode 100644 index 00000000000..7df274d8b92 --- /dev/null +++ b/llvm/lib/Target/AArch64/AArch64CallLowering.cpp @@ -0,0 +1,111 @@ +//===-- llvm/lib/Target/AArch64/AArch64CallLowering.cpp - Call lowering ---===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file implements the lowering of LLVM calls to machine code calls for +/// GlobalISel. +/// +//===----------------------------------------------------------------------===// + +#include "AArch64CallLowering.h" +#include "AArch64ISelLowering.h" + +#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" +#include "llvm/CodeGen/MachineInstrBuilder.h" + +using namespace llvm; +#ifdef LLVM_BUILD_GLOBAL_ISEL +# define EMIT_IMPLEMENTATION 1 +#else +# define EMIT_IMPLEMENTATION 0 +#endif + +AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI) + : CallLowering(&TLI) { +} + +bool AArch64CallLowering::LowerReturn(MachineIRBuilder &MIRBuilder, + const Value *Val, unsigned VReg) const { + if (!EMIT_IMPLEMENTATION) + return false; + + MachineInstr *Return = MIRBuilder.buildInstr(AArch64::RET_ReallyLR); + assert(Return && "Unable to build a return instruction?!"); + + assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg"); + if (VReg) { + assert(Val->getType()->isIntegerTy() && "Type not supported yet"); + unsigned Size = Val->getType()->getPrimitiveSizeInBits(); + assert((Size == 64 || Size == 32) && "Size not supported yet"); + unsigned ResReg = (Size == 32) ? AArch64::W0 : AArch64::X0; + // Set the insertion point to be right before Return. + MIRBuilder.setInstr(*Return, /* Before */ true); + MachineInstr *Copy = + MIRBuilder.buildInstr(TargetOpcode::COPY, ResReg, VReg); + (void)Copy; + assert(Copy->getNextNode() == Return && + "The insertion did not happen where we expected"); + MachineInstrBuilder(MIRBuilder.getMF(), Return) + .addReg(ResReg, RegState::Implicit); + } + return true; +} + +bool AArch64CallLowering::LowerFormalArguments( + MachineIRBuilder &MIRBuilder, const Function::ArgumentListType &Args, + const SmallVectorImpl<unsigned> &VRegs) const { + if (!EMIT_IMPLEMENTATION) + return false; + + MachineFunction &MF = MIRBuilder.getMF(); + const Function &F = *MF.getFunction(); + + SmallVector<CCValAssign, 16> ArgLocs; + CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); + + unsigned NumArgs = Args.size(); + Function::const_arg_iterator CurOrigArg = Args.begin(); + const AArch64TargetLowering &TLI = *getTLI<AArch64TargetLowering>(); + for (unsigned i = 0; i != NumArgs; ++i, ++CurOrigArg) { + MVT ValVT = MVT::getVT(CurOrigArg->getType()); + CCAssignFn *AssignFn = + TLI.CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false); + bool Res = + AssignFn(i, ValVT, ValVT, CCValAssign::Full, ISD::ArgFlagsTy(), CCInfo); + assert(!Res && "Call operand has unhandled type"); + (void)Res; + } + assert(ArgLocs.size() == Args.size() && + "We have a different number of location and args?!"); + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + + assert(VA.isRegLoc() && "Not yet implemented"); + // Transform the arguments in physical registers into virtual ones. + MIRBuilder.getMBB().addLiveIn(VA.getLocReg()); + MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg()); + + switch (VA.getLocInfo()) { + default: + llvm_unreachable("Unknown loc info!"); + case CCValAssign::Full: + break; + case CCValAssign::BCvt: + // We don't care about bitcast. + break; + case CCValAssign::AExt: + case CCValAssign::SExt: + case CCValAssign::ZExt: + // Zero/Sign extend the register. + assert(0 && "Not yet implemented"); + break; + } + } + return true; +} diff --git a/llvm/lib/Target/AArch64/AArch64CallLowering.h b/llvm/lib/Target/AArch64/AArch64CallLowering.h new file mode 100644 index 00000000000..449a237e913 --- /dev/null +++ b/llvm/lib/Target/AArch64/AArch64CallLowering.h @@ -0,0 +1,36 @@ +//===-- llvm/lib/Target/AArch64/AArch64CallLowering.h - Call lowering -----===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file describes how to lower LLVM calls to machine code calls. +/// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64CALLLOWERING +#define LLVM_LIB_TARGET_AARCH64_AARCH64CALLLOWERING + +#include "llvm/CodeGen/GlobalISel/CallLowering.h" + +namespace llvm { + +class AArch64TargetLowering; + +class AArch64CallLowering: public CallLowering { + public: + AArch64CallLowering(const AArch64TargetLowering &TLI); + + bool LowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, + unsigned VReg) const override; + bool + LowerFormalArguments(MachineIRBuilder &MIRBuilder, + const Function::ArgumentListType &Args, + const SmallVectorImpl<unsigned> &VRegs) const override; +}; +} // End of namespace llvm; +#endif diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index daff2d865a5..a18b7a61cc1 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -21,9 +21,6 @@ #include "MCTargetDesc/AArch64AddressingModes.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/CallingConvLower.h" -#ifdef LLVM_BUILD_GLOBAL_ISEL -# include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" -#endif #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -3395,81 +3392,6 @@ AArch64TargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, return DAG.getNode(AArch64ISD::RET_FLAG, DL, MVT::Other, RetOps); } -#ifdef LLVM_BUILD_GLOBAL_ISEL -bool AArch64TargetLowering::LowerReturn(MachineIRBuilder &MIRBuilder, - const Value *Val, unsigned VReg) const { - MachineInstr *Return = MIRBuilder.buildInstr(AArch64::RET_ReallyLR); - assert(Return && "Unable to build a return instruction?!"); - - assert(((Val && VReg) || (!Val && !VReg)) && "Return value without a vreg"); - if (VReg) { - assert(Val->getType()->isIntegerTy() && "Type not supported yet"); - unsigned Size = Val->getType()->getPrimitiveSizeInBits(); - assert((Size == 64 || Size == 32) && "Size not supported yet"); - unsigned ResReg = (Size == 32) ? AArch64::W0 : AArch64::X0; - // Set the insertion point to be right before Return. - MIRBuilder.setInstr(*Return, /* Before */ true); - MachineInstr *Copy = - MIRBuilder.buildInstr(TargetOpcode::COPY, ResReg, VReg); - (void)Copy; - assert(Copy->getNextNode() == Return && - "The insertion did not happen where we expected"); - MachineInstrBuilder(MIRBuilder.getMF(), Return) - .addReg(ResReg, RegState::Implicit); - } - return true; -} - -bool AArch64TargetLowering::LowerFormalArguments( - MachineIRBuilder &MIRBuilder, const Function::ArgumentListType &Args, - const SmallVectorImpl<unsigned> &VRegs) const { - MachineFunction &MF = MIRBuilder.getMF(); - const Function &F = *MF.getFunction(); - - SmallVector<CCValAssign, 16> ArgLocs; - CCState CCInfo(F.getCallingConv(), F.isVarArg(), MF, ArgLocs, F.getContext()); - - unsigned NumArgs = Args.size(); - Function::const_arg_iterator CurOrigArg = Args.begin(); - for (unsigned i = 0; i != NumArgs; ++i, ++CurOrigArg) { - MVT ValVT = MVT::getVT(CurOrigArg->getType()); - CCAssignFn *AssignFn = - CCAssignFnForCall(F.getCallingConv(), /*IsVarArg=*/false); - bool Res = - AssignFn(i, ValVT, ValVT, CCValAssign::Full, ISD::ArgFlagsTy(), CCInfo); - assert(!Res && "Call operand has unhandled type"); - (void)Res; - } - assert(ArgLocs.size() == Args.size() && - "We have a different number of location and args?!"); - for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { - CCValAssign &VA = ArgLocs[i]; - - assert(VA.isRegLoc() && "Not yet implemented"); - // Transform the arguments in physical registers into virtual ones. - MIRBuilder.getMBB().addLiveIn(VA.getLocReg()); - MIRBuilder.buildInstr(TargetOpcode::COPY, VRegs[i], VA.getLocReg()); - - switch (VA.getLocInfo()) { - default: - llvm_unreachable("Unknown loc info!"); - case CCValAssign::Full: - break; - case CCValAssign::BCvt: - // We don't care about bitcast. - break; - case CCValAssign::AExt: - case CCValAssign::SExt: - case CCValAssign::ZExt: - // Zero/Sign extend the register. - assert(0 && "Not yet implemented"); - break; - } - } - return true; -} -#endif - //===----------------------------------------------------------------------===// // Other Lowering Code //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 2879c030a1f..20c468e08de 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -452,15 +452,6 @@ private: const SmallVectorImpl<SDValue> &OutVals, SDLoc DL, SelectionDAG &DAG) const override; -#ifdef LLVM_BUILD_GLOBAL_ISEL - bool LowerReturn(MachineIRBuilder &MIRBuiler, const Value *Val, - unsigned VReg) const override; - bool - LowerFormalArguments(MachineIRBuilder &MIRBuilder, - const Function::ArgumentListType &Args, - const SmallVectorImpl<unsigned> &VRegs) const override; -#endif - SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; SDValue LowerDarwinGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index f6ee8cf47a6..2c7f5c0f470 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -57,7 +57,14 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, StrictAlign(false), ReserveX18(TT.isOSDarwin()), IsLittle(LittleEndian), CPUString(CPU), TargetTriple(TT), FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS)), TSInfo(), - TLInfo(TM, *this) {} + TLInfo(TM, *this), CallLoweringInfo(nullptr) {} + +const CallLowering * +AArch64Subtarget::getCallLowering() const { + if (!CallLoweringInfo) + CallLoweringInfo.reset(new AArch64CallLowering(TLInfo)); + return CallLoweringInfo.get(); +} /// ClassifyGlobalReference - Find the target operand flags that describe /// how a global value should be referenced for the current subtarget. diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index d30542225d0..f099637279b 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -14,6 +14,7 @@ #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H #define LLVM_LIB_TARGET_AARCH64_AARCH64SUBTARGET_H +#include "AArch64CallLowering.h" #include "AArch64FrameLowering.h" #include "AArch64ISelLowering.h" #include "AArch64InstrInfo.h" @@ -81,6 +82,7 @@ protected: AArch64InstrInfo InstrInfo; AArch64SelectionDAGInfo TSInfo; AArch64TargetLowering TLInfo; + mutable std::unique_ptr<AArch64CallLowering> CallLoweringInfo; private: /// initializeSubtargetDependencies - Initializes using CPUString and the /// passed in feature string so that we can use initializer lists for @@ -107,6 +109,7 @@ public: const AArch64RegisterInfo *getRegisterInfo() const override { return &getInstrInfo()->getRegisterInfo(); } + const CallLowering *getCallLowering() const override; const Triple &getTargetTriple() const { return TargetTriple; } bool enableMachineScheduler() const override { return true; } bool enablePostRAScheduler() const override { diff --git a/llvm/lib/Target/AArch64/CMakeLists.txt b/llvm/lib/Target/AArch64/CMakeLists.txt index f26327ff84a..4e91dbb9bbc 100644 --- a/llvm/lib/Target/AArch64/CMakeLists.txt +++ b/llvm/lib/Target/AArch64/CMakeLists.txt @@ -20,6 +20,7 @@ add_llvm_target(AArch64CodeGen AArch64AdvSIMDScalarPass.cpp AArch64AsmPrinter.cpp AArch64BranchRelaxation.cpp + AArch64CallLowering.cpp AArch64CleanupLocalDynamicTLSPass.cpp AArch64CollectLOH.cpp AArch64ConditionalCompares.cpp |
