diff options
Diffstat (limited to 'llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp index 583a07f6a7b..b4a554e0658 100644 --- a/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp +++ b/llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp @@ -188,6 +188,10 @@ static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, unsigned RegNo, uint64_t Addr, const void *Decoder); +static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, + uint32_t insn, + uint64_t Address, + const void *Decoder); template<int Bits> static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder); @@ -1649,6 +1653,22 @@ static DecodeStatus DecodeXSeqPairsClassRegisterClass(MCInst &Inst, RegNo, Addr, Decoder); } +static DecodeStatus DecodeSVELogicalImmInstruction(llvm::MCInst &Inst, + uint32_t insn, + uint64_t Addr, + const void *Decoder) { + unsigned Zdn = fieldFromInstruction(insn, 0, 5); + unsigned imm = fieldFromInstruction(insn, 5, 13); + if (!AArch64_AM::isValidDecodeLogicalImmediate(imm, 64)) + return Fail; + + // The same (tied) operand is added twice to the instruction. + DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); + DecodeZPRRegisterClass(Inst, Zdn, Addr, Decoder); + Inst.addOperand(MCOperand::createImm(imm)); + return Success; +} + template<int Bits> static DecodeStatus DecodeSImm(llvm::MCInst &Inst, uint64_t Imm, uint64_t Address, const void *Decoder) { |
