diff options
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp | 27 |
1 files changed, 0 insertions, 27 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp index 9cf9cd8b8e2..58624f24ec0 100644 --- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -1180,33 +1180,6 @@ bool AArch64InstructionSelector::select(MachineInstr &I) const { return selectCopy(I, TII, MRI, TRI, RBI); return false; - case TargetOpcode::G_FPEXT: { - if (MRI.getType(I.getOperand(0).getReg()) != LLT::scalar(64)) { - DEBUG(dbgs() << "G_FPEXT to type " << Ty - << ", expected: " << LLT::scalar(64) << '\n'); - return false; - } - - if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(32)) { - DEBUG(dbgs() << "G_FPEXT from type " << Ty - << ", expected: " << LLT::scalar(32) << '\n'); - return false; - } - - const unsigned DefReg = I.getOperand(0).getReg(); - const RegisterBank &RB = *RBI.getRegBank(DefReg, MRI, TRI); - - if (RB.getID() != AArch64::FPRRegBankID) { - DEBUG(dbgs() << "G_FPEXT on bank: " << RB << ", expected: FPR\n"); - return false; - } - - I.setDesc(TII.get(AArch64::FCVTDSr)); - constrainSelectedInstRegOperands(I, TII, TRI, RBI); - - return true; - } - case TargetOpcode::G_SELECT: { if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) { DEBUG(dbgs() << "G_SELECT cond has type: " << Ty |
