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Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp')
-rw-r--r--llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp4
1 files changed, 1 insertions, 3 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 872f99cf41d..b95adaf7eb1 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -733,9 +733,7 @@ SDNode *AArch64DAGToDAGISel::SelectVTBL(SDNode *N, unsigned NumVecs,
// Check the element of look up table is 64-bit or not
unsigned Vec0Idx = IsExt ? 2 : 1;
- SDValue V0 = N->getOperand(Vec0Idx + 0);
- EVT VT = V0.getValueType();
- assert(!VT.is64BitVector() &&
+ assert(!N->getOperand(Vec0Idx + 0).getValueType().is64BitVector() &&
"The element of lookup table for vtbl and vtbx must be 128-bit");
// Check the return value type is 64-bit or not
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