diff options
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64FastISel.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64FastISel.cpp | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index 07c84cdda5d..619dfd66d1c 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -2871,11 +2871,14 @@ bool AArch64FastISel::selectRet(const Instruction *I) { const Value *RV = Ret->getOperand(0); // Don't bother handling odd stuff for now. - if (VA.getLocInfo() != CCValAssign::Full) + if ((VA.getLocInfo() != CCValAssign::Full) && + (VA.getLocInfo() != CCValAssign::BCvt)) return false; + // Only handle register returns for now. if (!VA.isRegLoc()) return false; + unsigned Reg = getRegForValue(RV); if (Reg == 0) return false; @@ -2891,12 +2894,14 @@ bool AArch64FastISel::selectRet(const Instruction *I) { return false; // Vectors (of > 1 lane) in big endian need tricky handling. - if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1) + if (RVEVT.isVector() && RVEVT.getVectorNumElements() > 1 && + !Subtarget->isLittleEndian()) return false; MVT RVVT = RVEVT.getSimpleVT(); if (RVVT == MVT::f128) return false; + MVT DestVT = VA.getValVT(); // Special handling for extended integers. if (RVVT != DestVT) { |
