diff options
Diffstat (limited to 'llvm/lib/Target/AArch64/AArch64FastISel.cpp')
| -rw-r--r-- | llvm/lib/Target/AArch64/AArch64FastISel.cpp | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/llvm/lib/Target/AArch64/AArch64FastISel.cpp b/llvm/lib/Target/AArch64/AArch64FastISel.cpp index b7738c3e33a..43a3ae77a17 100644 --- a/llvm/lib/Target/AArch64/AArch64FastISel.cpp +++ b/llvm/lib/Target/AArch64/AArch64FastISel.cpp @@ -307,7 +307,7 @@ public: #include "AArch64GenCallingConv.inc" -/// \brief Check if the sign-/zero-extend will be a noop. +/// Check if the sign-/zero-extend will be a noop. static bool isIntExtFree(const Instruction *I) { assert((isa<ZExtInst>(I) || isa<SExtInst>(I)) && "Unexpected integer extend instruction."); @@ -326,7 +326,7 @@ static bool isIntExtFree(const Instruction *I) { return false; } -/// \brief Determine the implicit scale factor that is applied by a memory +/// Determine the implicit scale factor that is applied by a memory /// operation for a given value type. static unsigned getImplicitScaleFactor(MVT VT) { switch (VT.SimpleTy) { @@ -535,7 +535,7 @@ unsigned AArch64FastISel::fastMaterializeFloatZero(const ConstantFP* CFP) { return fastEmitInst_r(Opc, TLI.getRegClassFor(VT), ZReg, /*IsKill=*/true); } -/// \brief Check if the multiply is by a power-of-2 constant. +/// Check if the multiply is by a power-of-2 constant. static bool isMulPowOf2(const Value *I) { if (const auto *MI = dyn_cast<MulOperator>(I)) { if (const auto *C = dyn_cast<ConstantInt>(MI->getOperand(0))) @@ -964,7 +964,7 @@ bool AArch64FastISel::isTypeLegal(Type *Ty, MVT &VT) { return TLI.isTypeLegal(VT); } -/// \brief Determine if the value type is supported by FastISel. +/// Determine if the value type is supported by FastISel. /// /// FastISel for AArch64 can handle more value types than are legal. This adds /// simple value type such as i1, i8, and i16. @@ -1524,7 +1524,7 @@ unsigned AArch64FastISel::emitAdd(MVT RetVT, const Value *LHS, const Value *RHS, IsZExt); } -/// \brief This method is a wrapper to simplify add emission. +/// This method is a wrapper to simplify add emission. /// /// First try to emit an add with an immediate operand using emitAddSub_ri. If /// that fails, then try to materialize the immediate into a register and use @@ -2254,7 +2254,7 @@ static AArch64CC::CondCode getCompareCC(CmpInst::Predicate Pred) { } } -/// \brief Try to emit a combined compare-and-branch instruction. +/// Try to emit a combined compare-and-branch instruction. bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) { assert(isa<CmpInst>(BI->getCondition()) && "Expected cmp instruction"); const CmpInst *CI = cast<CmpInst>(BI->getCondition()); @@ -2607,7 +2607,7 @@ bool AArch64FastISel::selectCmp(const Instruction *I) { return true; } -/// \brief Optimize selects of i1 if one of the operands has a 'true' or 'false' +/// Optimize selects of i1 if one of the operands has a 'true' or 'false' /// value. bool AArch64FastISel::optimizeSelect(const SelectInst *SI) { if (!SI->getType()->isIntegerTy(1)) @@ -3322,7 +3322,7 @@ bool AArch64FastISel::tryEmitSmallMemCpy(Address Dest, Address Src, return true; } -/// \brief Check if it is possible to fold the condition from the XALU intrinsic +/// Check if it is possible to fold the condition from the XALU intrinsic /// into the user. The condition code will only be updated on success. bool AArch64FastISel::foldXALUIntrinsic(AArch64CC::CondCode &CC, const Instruction *I, |
