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-rw-r--r--llvm/lib/CodeGen/PrologEpilogInserter.cpp8
-rw-r--r--llvm/lib/CodeGen/RegAllocBigBlock.cpp8
-rw-r--r--llvm/lib/CodeGen/RegAllocLocal.cpp8
-rw-r--r--llvm/lib/CodeGen/RegAllocSimple.cpp7
-rw-r--r--llvm/lib/CodeGen/RegisterScavenging.cpp6
-rw-r--r--llvm/lib/CodeGen/VirtRegMap.cpp20
6 files changed, 36 insertions, 21 deletions
diff --git a/llvm/lib/CodeGen/PrologEpilogInserter.cpp b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
index d1f796d47d1..9c3912350f2 100644
--- a/llvm/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/llvm/lib/CodeGen/PrologEpilogInserter.cpp
@@ -243,7 +243,8 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) {
return;
const MRegisterInfo *RegInfo = Fn.getTarget().getRegisterInfo();
-
+ const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
+
// Now that we have a stack slot for each register to be saved, insert spill
// code into the entry block.
MachineBasicBlock *MBB = Fn.begin();
@@ -254,13 +255,12 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) {
MBB->addLiveIn(CSI[i].getReg());
// Insert the spill to the stack frame.
- RegInfo->storeRegToStackSlot(*MBB, I, CSI[i].getReg(), true,
+ TII.storeRegToStackSlot(*MBB, I, CSI[i].getReg(), true,
CSI[i].getFrameIdx(), CSI[i].getRegClass());
}
}
// Add code to restore the callee-save registers in each exiting block.
- const TargetInstrInfo &TII = *Fn.getTarget().getInstrInfo();
for (MachineFunction::iterator FI = Fn.begin(), E = Fn.end(); FI != E; ++FI)
// If last instruction is a return instruction, add an epilogue.
if (!FI->empty() && TII.isReturn(FI->back().getOpcode())) {
@@ -282,7 +282,7 @@ void PEI::saveCalleeSavedRegisters(MachineFunction &Fn) {
// that preceed it.
if (!RegInfo->restoreCalleeSavedRegisters(*MBB, I, CSI)) {
for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
- RegInfo->loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
+ TII.loadRegFromStackSlot(*MBB, I, CSI[i].getReg(),
CSI[i].getFrameIdx(),
CSI[i].getRegClass());
assert(I != MBB->begin() &&
diff --git a/llvm/lib/CodeGen/RegAllocBigBlock.cpp b/llvm/lib/CodeGen/RegAllocBigBlock.cpp
index 5c894729a7e..4d34a9ac6d1 100644
--- a/llvm/lib/CodeGen/RegAllocBigBlock.cpp
+++ b/llvm/lib/CodeGen/RegAllocBigBlock.cpp
@@ -319,6 +319,9 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
" the intended one.");
DOUT << " Spilling register " << RegInfo->getName(PhysReg)
<< " containing %reg" << VirtReg;
+
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+
if (!isVirtRegModified(VirtReg))
DOUT << " which has not been modified, so no store necessary!";
@@ -329,7 +332,7 @@ void RABigBlock::spillVirtReg(MachineBasicBlock &MBB,
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DOUT << " to stack slot #" << FrameIndex;
- RegInfo->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
+ TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
++NumStores; // Update statistics
}
@@ -542,7 +545,8 @@ MachineInstr *RABigBlock::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI
<< RegInfo->getName(PhysReg) << "\n";
// Add move instruction(s)
- RegInfo->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+ TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
MF->getRegInfo().setPhysRegUsed(PhysReg);
diff --git a/llvm/lib/CodeGen/RegAllocLocal.cpp b/llvm/lib/CodeGen/RegAllocLocal.cpp
index 8c38cd06f93..251d175ea6f 100644
--- a/llvm/lib/CodeGen/RegAllocLocal.cpp
+++ b/llvm/lib/CodeGen/RegAllocLocal.cpp
@@ -276,6 +276,9 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB,
" the intended one.");
DOUT << " Spilling register " << MRI->getName(PhysReg)
<< " containing %reg" << VirtReg;
+
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+
if (!isVirtRegModified(VirtReg))
DOUT << " which has not been modified, so no store necessary!";
@@ -286,7 +289,7 @@ void RALocal::spillVirtReg(MachineBasicBlock &MBB,
const TargetRegisterClass *RC = MF->getRegInfo().getRegClass(VirtReg);
int FrameIndex = getStackSpaceFor(VirtReg, RC);
DOUT << " to stack slot #" << FrameIndex;
- MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
+ TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIndex, RC);
++NumStores; // Update statistics
}
@@ -495,7 +498,8 @@ MachineInstr *RALocal::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
<< MRI->getName(PhysReg) << "\n";
// Add move instruction(s)
- MRI->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+ TII->loadRegFromStackSlot(MBB, MI, PhysReg, FrameIndex, RC);
++NumLoads; // Update statistics
MF->getRegInfo().setPhysRegUsed(PhysReg);
diff --git a/llvm/lib/CodeGen/RegAllocSimple.cpp b/llvm/lib/CodeGen/RegAllocSimple.cpp
index a60c63c28e4..7ea96233037 100644
--- a/llvm/lib/CodeGen/RegAllocSimple.cpp
+++ b/llvm/lib/CodeGen/RegAllocSimple.cpp
@@ -144,7 +144,8 @@ unsigned RegAllocSimple::reloadVirtReg(MachineBasicBlock &MBB,
// Add move instruction(s)
++NumLoads;
- MRI->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+ TII->loadRegFromStackSlot(MBB, I, PhysReg, FrameIdx, RC);
return PhysReg;
}
@@ -152,11 +153,13 @@ void RegAllocSimple::spillVirtReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
unsigned VirtReg, unsigned PhysReg) {
const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(VirtReg);
+ const TargetInstrInfo* TII = MBB.getParent()->getTarget().getInstrInfo();
+
int FrameIdx = getStackSpaceFor(VirtReg, RC);
// Add move instruction(s)
++NumStores;
- MRI->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
+ TII->storeRegToStackSlot(MBB, I, PhysReg, true, FrameIdx, RC);
}
diff --git a/llvm/lib/CodeGen/RegisterScavenging.cpp b/llvm/lib/CodeGen/RegisterScavenging.cpp
index d881b196bd4..9e917bd0bab 100644
--- a/llvm/lib/CodeGen/RegisterScavenging.cpp
+++ b/llvm/lib/CodeGen/RegisterScavenging.cpp
@@ -72,7 +72,7 @@ void RegScavenger::restoreScavengedReg() {
if (!ScavengedReg)
return;
- RegInfo->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
+ TII->loadRegFromStackSlot(*MBB, MBBI, ScavengedReg,
ScavengingFrameIndex, ScavengedRC);
MachineBasicBlock::iterator II = prior(MBBI);
RegInfo->eliminateFrameIndex(II, 0, this);
@@ -276,13 +276,13 @@ unsigned RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
if (ScavengedReg != 0) {
// First restore previously scavenged register.
- RegInfo->loadRegFromStackSlot(*MBB, I, ScavengedReg,
+ TII->loadRegFromStackSlot(*MBB, I, ScavengedReg,
ScavengingFrameIndex, ScavengedRC);
MachineBasicBlock::iterator II = prior(I);
RegInfo->eliminateFrameIndex(II, SPAdj, this);
}
- RegInfo->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
+ TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC);
MachineBasicBlock::iterator II = prior(I);
RegInfo->eliminateFrameIndex(II, SPAdj, this);
ScavengedReg = SReg;
diff --git a/llvm/lib/CodeGen/VirtRegMap.cpp b/llvm/lib/CodeGen/VirtRegMap.cpp
index dc215180c2a..65927329634 100644
--- a/llvm/lib/CodeGen/VirtRegMap.cpp
+++ b/llvm/lib/CodeGen/VirtRegMap.cpp
@@ -173,7 +173,8 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
DOUT << "********** REWRITE MACHINE CODE **********\n";
DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
const TargetMachine &TM = MF.getTarget();
- const MRegisterInfo &MRI = *TM.getRegisterInfo();
+ const TargetInstrInfo &TII = *TM.getInstrInfo();
+
// LoadedRegs - Keep track of which vregs are loaded, so that we only load
// each vreg once (in the case where a spilled vreg is used by multiple
@@ -202,14 +203,14 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
if (MO.isUse() &&
std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
== LoadedRegs.end()) {
- MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
+ TII.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
LoadedRegs.push_back(VirtReg);
++NumLoads;
DOUT << '\t' << *prior(MII);
}
if (MO.isDef()) {
- MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
+ TII.storeRegToStackSlot(MBB, next(MII), PhysReg, true,
StackSlot, RC);
++NumStores;
}
@@ -645,6 +646,9 @@ namespace {
BitVector &RegKills,
std::vector<MachineOperand*> &KillOps,
VirtRegMap &VRM) {
+ const TargetInstrInfo* TII = MI->getParent()->getParent()->getTarget()
+ .getInstrInfo();
+
if (Reuses.empty()) return PhysReg; // This is most often empty.
for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
@@ -693,7 +697,7 @@ namespace {
VRM.getReMaterializedMI(NewOp.VirtReg));
++NumReMats;
} else {
- MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
+ TII->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
NewOp.StackSlotOrReMat, AliasRC);
// Any stores to this stack slot are not dead anymore.
MaybeDeadStores[NewOp.StackSlotOrReMat] = NULL;
@@ -876,7 +880,7 @@ void LocalSpiller::SpillRegToStackSlot(MachineBasicBlock &MBB,
BitVector &RegKills,
std::vector<MachineOperand*> &KillOps,
VirtRegMap &VRM) {
- MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
+ TII->storeRegToStackSlot(MBB, next(MII), PhysReg, true, StackSlot, RC);
DOUT << "Store:\t" << *next(MII);
// If there is a dead store to this stack slot, nuke it now.
@@ -979,7 +983,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
++NumReMats;
} else {
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
- MRI->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg),
+ TII->loadRegFromStackSlot(MBB, &MI, Phys, VRM.getStackSlot(VirtReg),
RC);
++NumLoads;
}
@@ -1002,7 +1006,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
unsigned Phys = VRM.getPhys(VirtReg);
int StackSlot = VRM.getStackSlot(VirtReg);
- MRI->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
+ TII->storeRegToStackSlot(MBB, next(MII), Phys, isKill, StackSlot, RC);
MachineInstr *StoreMI = next(MII);
DOUT << "Store:\t" << StoreMI;
VRM.virtFolded(VirtReg, StoreMI, VirtRegMap::isMod);
@@ -1218,7 +1222,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
++NumReMats;
} else {
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
- MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
+ TII->loadRegFromStackSlot(MBB, &MI, PhysReg, SSorRMId, RC);
++NumLoads;
}
// This invalidates PhysReg.
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