diff options
Diffstat (limited to 'llvm/lib/CodeGen')
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 2 | ||||
| -rw-r--r-- | llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp | 60 |
2 files changed, 12 insertions, 50 deletions
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index fbca421a22c..c581439cc2b 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -89,7 +89,7 @@ bool IRTranslator::translateBr(const Instruction &Inst) { if (BrInst.isUnconditional()) { const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getOperand(0)); MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt); - MIRBuilder.buildInstr(TargetOpcode::G_BR, LLT{*BrTgt.getType()}, TgtBB); + MIRBuilder.buildBr(TgtBB); } else { assert(0 && "Not yet implemented"); } diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index f18467c4bb4..fb9b296e8ac 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -56,12 +56,14 @@ MachineBasicBlock::iterator MachineIRBuilder::getInsertPt() { //------------------------------------------------------------------------------ // Build instruction variants. //------------------------------------------------------------------------------ -MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, LLT Ty) { + +MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, ArrayRef<LLT> Tys) { MachineInstr *NewMI = BuildMI(getMF(), DL, getTII().get(Opcode)); - if (Ty.isValid()) { + if (Tys.size() > 0) { assert(isPreISelGenericOpcode(Opcode) && "Only generic instruction can have a type"); - NewMI->setType(Ty); + for (unsigned i = 0; i < Tys.size(); ++i) + NewMI->setType(Tys[i], i); } else assert(!isPreISelGenericOpcode(Opcode) && "Generic instruction must have a type"); @@ -69,52 +71,6 @@ MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, LLT Ty) { return NewMI; } -MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res, - unsigned Op0, unsigned Op1) { - return buildInstr(Opcode, LLT{}, Res, Op0, Op1); -} - -MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, LLT Ty, - unsigned Res, unsigned Op0, - unsigned Op1) { - MachineInstr *NewMI = buildInstr(Opcode, Ty); - MachineInstrBuilder(getMF(), NewMI) - .addReg(Res, RegState::Define) - .addReg(Op0) - .addReg(Op1); - return NewMI; -} - -MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, ArrayRef<LLT> Tys, - unsigned Res, unsigned Op0) { - MachineInstr *NewMI = buildInstr(Opcode, Tys[0]); - for (unsigned i = 1; i < Tys.size(); ++i) - NewMI->setType(Tys[i], i); - - MachineInstrBuilder(getMF(), NewMI) - .addReg(Res, RegState::Define) - .addReg(Op0); - return NewMI; -} - -MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res, - unsigned Op0) { - MachineInstr *NewMI = buildInstr(Opcode, LLT{}); - MachineInstrBuilder(getMF(), NewMI).addReg(Res, RegState::Define).addReg(Op0); - return NewMI; -} - -MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode) { - return buildInstr(Opcode, LLT{}); -} - -MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, LLT Ty, - MachineBasicBlock &BB) { - MachineInstr *NewMI = buildInstr(Opcode, Ty); - MachineInstrBuilder(getMF(), NewMI).addMBB(&BB); - return NewMI; -} - MachineInstr *MachineIRBuilder::buildFrameIndex(LLT Ty, unsigned Res, int Idx) { MachineInstr *NewMI = buildInstr(TargetOpcode::G_FRAME_INDEX, Ty); auto MIB = MachineInstrBuilder(getMF(), NewMI); @@ -128,6 +84,12 @@ MachineInstr *MachineIRBuilder::buildAdd(LLT Ty, unsigned Res, unsigned Op0, return buildInstr(TargetOpcode::G_ADD, Ty, Res, Op0, Op1); } +MachineInstr *MachineIRBuilder::buildBr(MachineBasicBlock &Dest) { + MachineInstr *NewMI = buildInstr(TargetOpcode::G_BR, LLT::unsized()); + MachineInstrBuilder(getMF(), NewMI).addMBB(&Dest); + return NewMI; +} + MachineInstr *MachineIRBuilder::buildExtract(LLT Ty, ArrayRef<unsigned> Results, unsigned Src, ArrayRef<unsigned> Indexes) { |
