1 files changed, 34 insertions, 8 deletions

diff --git a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
index ee00894ccd9..1a4ce00044a 100644
--- a/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/RegisterBankInfo.cpp
@@ -21,6 +21,7 @@
 #include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetOpcodes.h"
 #include "llvm/Target/TargetRegisterInfo.h"
+#include "llvm/Target/TargetSubtargetInfo.h"
 
 #include <algorithm> // For std::max.
 
@@ -30,6 +31,37 @@ using namespace llvm;
 
 const unsigned RegisterBankInfo::DefaultMappingID = UINT_MAX;
 
+/// Get the size in bits of the \p OpIdx-th operand of \p MI.
+///
+/// \pre \p MI is part of a basic block and this basic block is part
+/// of a function.
+static unsigned getSizeInBits(const MachineInstr &MI, unsigned OpIdx) {
+  unsigned Reg = MI.getOperand(OpIdx).getReg();
+  const TargetRegisterClass *RC = nullptr;
+  if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
+    const TargetSubtargetInfo &STI =
+        MI.getParent()->getParent()->getSubtarget();
+    const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
+    // The size is not directly available for physical registers.
+    // Instead, we need to access a register class that contains Reg and
+    // get the size of that register class.
+    RC = TRI.getMinimalPhysRegClass(Reg);
+  } else {
+    const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
+    unsigned RegSize = MRI.getSize(Reg);
+    // If Reg is not a generic register, query the register class to
+    // get its size.
+    if (RegSize)
+      return RegSize;
+    RC = MRI.getRegClass(Reg);
+  }
+  assert(RC && "Unable to deduce the register class");
+  return RC->getSize() * 8;
+}
+
+//------------------------------------------------------------------------------
+// RegisterBankInfo implementation.
+//------------------------------------------------------------------------------
 RegisterBankInfo::RegisterBankInfo(unsigned NumRegBanks)
     : NumRegBanks(NumRegBanks) {
   RegBanks.reset(new RegisterBank[NumRegBanks]);
@@ -245,7 +277,6 @@ void RegisterBankInfo::ValueMapping::verify(unsigned ExpectedBitWidth) const {
 void RegisterBankInfo::InstructionMapping::verify(
     const MachineInstr &MI) const {
   // Check that all the register operands are properly mapped.
-  const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
   // Check the constructor invariant.
   assert(NumOperands == MI.getNumOperands() &&
          "NumOperands must match, see constructor");
@@ -257,14 +288,9 @@ void RegisterBankInfo::InstructionMapping::verify(
              "We should not care about non-reg mapping");
       continue;
     }
-    unsigned Reg = MO.getReg();
     // Register size in bits.
-    // This size must match what the mapping expect.
-    unsigned RegSize = MRI.getSize(Reg);
-    // If Reg is not a generic register, query the register class to
-    // get its size.
-    if (!RegSize)
-      RegSize = MRI.getRegClass(Reg)->getSize() * 8;
+    // This size must match what the mapping expects.
+    unsigned RegSize = getSizeInBits(MI, Idx);
     MOMapping.verify(RegSize);
   }
 }